Results 81 to 90 of about 289,843 (203)
Exploring Many-Core Design Templates for FPGAs and ASICs
International Journal of Reconfigurable Computing, 2012 We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL.
Ilia Lebedev +7 more
doaj +1 more source
Fatigue‐Driven Adaptive Assistance for a Semi‐Active Upper‐Limb Occupational Exoskeleton
Advanced Intelligent Systems, EarlyView.Physical fatigue during a physical activity is estimated in real time to enable adaptive exoskeleton assistance. By continuously adjusting the level of support according to the user’s fatigue, this approach reduces physical demand and provides a pathway toward personalized exoskeleton assistance.
Seemab Zakir +6 more
wiley +1 more source
Analysis of an 8-bit Serial Rijndael-256 FPGA Implementation
IEEE AccessThis paper presents an FPGA 8-bit serial implementation of a 256-bit message and key Rijndael encryption scheme (Rijndael-256). The main reason to implement this algorithm employing such architecture comes from the NIST proposal to standardize this ...
Carlos Fernandez-Garcia +1 more
doaj +1 more source
Comparative Analysis among DSP and FPGA-based Control Capabilities in PWM Power Converters [PDF]
, 2004 PWM power converters are close to be mature for standard diffusion. New FPGA technologies could now realise at best the digital control key-points: flexible performance and time to market.
Fratta, Antonino +7 more
core +1 more source
Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders
International Journal of Circuit Theory and Applications, EarlyView.A balanced parallel CPA‐tree architecture with CSLA reduces the critical‐path delay of multi‐operand addition while preserving structural regularity. ASIC results demonstrate delay reductions of up to 34% with low area overhead, providing an efficient and scalable solution for high‐performance arithmetic.
Lucas R. Kieslich +3 more
wiley +1 more source
IMPLEMENTATION OF FPGA-BASED RISC FOR LNS ARITHMETIC BY SOFTWARE & HARDWARE
Journal of Engineering, 2006 ield Programmable Gate Arrays (FPGAs) have some difficulty with the implementation of deating-point operations. In particular, devoting the large number of slices needed by floating-point multipliers prohibits incorporating floating point into smaller ...
N. H. Abbas
doaj +1 more source
Energy Science &Engineering, EarlyView.This paper introduces the probabilistic fractional‐order Mam‐KAN (PFO‐Mam‐KAN) controller, a physics‐informed gray‐box framework for real‐time battery state‐of‐charge estimation. By unifying efficient Mamba encoders with uncertainty‐aware fractional physics, it achieves superior 0.31% RMSE accuracy and robust grid‐support operation under dynamic ...
Arun Kumar Rawat +2 more
wiley +1 more source
Fast FPGA Implementations of Diffie-Hellman on the Kummer Surface of a Genus-2 Curve
Transactions on Cryptographic Hardware and Embedded Systems, 2018 We present the first hardware implementations of Diffie-Hellman key exchange based on the Kummer surface of Gaudry and Schost’s genus-2 curve targeting a 128-bit security level.
Philipp Koppermann +3 more
doaj +1 more source
Energy Science &Engineering, EarlyView.A Tri‐Meta Hybrid DOA–CSA–WOA Maximum Power Point Tracking controller is developed to enhance photovoltaic system performance. The proposed approach achieves higher tracking efficiency, faster convergence, and robust operation under dynamic irradiance and partial shading conditions.
Ali Abbas +6 more
wiley +1 more source
Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
IEEE Access, 2019 Deep learning techniques have been gaining prominence in the research world in the past years; however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications.
Maria G. F. Coutinho +2 more
doaj +1 more source