Results 11 to 20 of about 289,843 (203)
Efficient FPGA implementation and power modelling of image and signal processing IP cores [PDF]
, 2007 This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.Field Programmable Gate Arrays (FPGAs) are the technology of choice in a number ofimage and signal processing application areas such as consumer ...
Chandrasekaran, Shrutisagar
core +7 more sources
Efficient architectures and power modelling of multiresolution analysis algorithms on FPGA [PDF]
, 2011 This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.In the past two decades, there has been huge amount of interest in Multiresolution Analysis Algorithms (MAAs) and their applications.
Sazish, Abdul Naser
core +7 more sources
FPGA Realizations of Chaotic Epidemic and Disease Models Including Covid-19
IEEE Access, 2021 The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic ...
M. Elnawawy +7 more
doaj +1 more source
Parallel Implementation of K-Means Algorithm on FPGA
IEEE Access, 2020 The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical,
Leonardo A. Dias +2 more
doaj +1 more source
International Journal of Reconfigurable Computing, 2012 K-means clustering has been widely used in processing large datasets in many fields of studies. Advancement in many data collection techniques has been generating enormous amounts of data, leaving scientists with the challenging task of processing them ...
Hanaa M. Hussain +4 more
doaj +1 more source
Hardware acceleration of number theoretic transform for zk‐SNARK
Engineering Reports, EarlyView., 2023 An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao +6 more
wiley +1 more source
Energies, 2019 Motivated by the effects of deregulation over power quality and the subsequent need of new types of measurements, this paper assesses different implementations of an estimate for the spectral kurtosis, considered as a low-level harmonic detection ...
María-Ángeles Cifredo-Chacón +3 more
doaj +1 more source
A fully-mapped and energy-efficient FPGA accelerator for dual-function AI-based analysis of ECG
Frontiers in Physiology, 2023 In this paper, a fully-mapped field programmable gate array (FPGA) accelerator is proposed for artificial intelligence (AI)-based analysis of electrocardiogram (ECG). It consists of a fully-mapped 1-D convolutional neural network (CNN) and a fully-mapped
Wenhan Liu +6 more
doaj +1 more source
High-Speed FPGA 10's Complement Adders-Subtractors
International Journal of Reconfigurable Computing, 2010 This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms.
G. Bioul +3 more
doaj +1 more source
A biophysically accurate floating point somatic neuroprocessor [PDF]
, 2009 Biophysically accurate neuron models have emerged as a very useful tool for neuroscience research. These models are based on solving differential equations that govern membrane potentials and spike generation.
Edward Regan +9 more
core +1 more source