Results 31 to 40 of about 35,500 (242)
Constructing cluster of simple FPGA boards for cryptologic computations [PDF]
, 2012 In this paper, we propose an FPGA cluster infrastructure, which can be utilized in implementing cryptanalytic attacks and accelerating cryptographic operations.
Doroz, Yarkin +3 more
core +1 more source
SIFO: Secure Computational Infrastructure Using FPGA Overlays
International Journal of Reconfigurable Computing, 2019 Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost.
Xin Fang +2 more
doaj +1 more source
IEEE Access, 2016 In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl-Cocke-Jelinek-Raviv
An Li +4 more
doaj +1 more source
Platform for Testing and Evaluation of PUF and TRNG Implementations in FPGAs [PDF]
, 2016 Implementation of cryptographic primitives like Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) depends significantly on the underlying hardware.
Drutarovsky, Milos +3 more
core +1 more source
PGA HPC Implementation of Microtubule Brownian Dynamics Simulations
Труды Института системного программирования РАН, 2018 This paper presents high performance simulation of microtubule molecular dynamics implemented on Xilinx Virtex-7 FPGA using high level synthesis tool Vivado HLS.
Y. A. Rumyanstev +6 more
doaj +1 more source
, 2018 Hardware accelerations of deep learning systems have been extensively investigated in industry and academia. The aim of this paper is to achieve ultra-high energy efficiency and performance for hardware implementations of deep neural networks (DNNs).
Ding, Caiwen +10 more
core +1 more source
High performance FPGA implementation of the mersenne twister [PDF]
, 2008 Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twister is presented. The proposed architecture has the smallest footprint of all
Amira, A, Chandrasekaran, S
core +1 more source
Raising the Abstraction Level of a Deep Learning Design on FPGAs
IEEE Access, 2020 Autonomous and intelligent systems based on deep learning, continuously attract the attention of researchers and engineers. With the progress on the application of deep learning for modern applications arises the challenge of reaching real-time ...
Dario Baptista +2 more
doaj +1 more source
Kecerdasan matematik-logik dalam kalangan pelajar sarjana Pendidikan Teknik dan Vokasional UTHM [PDF]
, 2013 Kecerdasan matematik-logik sering dikaitkan dengan penguasaan pelajar dalam subjek matematik. Pencapaian pelajar, khususnya pelajar Sarjana Pendidikan Teknik dan Vokasional, Universiti Tun Hussein Onn Malaysia (UTHM) dalam kursus Statistik dalam ...
Mohd Zain, Noorhafiezah
core +1 more source
Visual Spike-based Convolution Processing with a Cellular Automata Architecture [PDF]
, 2010 this paper presents a first approach for implementations which fuse the Address-Event-Representation (AER) processing with the Cellular Automata using FPGA and AER-tools.
Cerdá, J. +5 more
core +1 more source