Results 21 to 30 of about 289,843 (203)

Numerical Simulations and FPGA Implementations of Fractional-Order Systems Based on Product Integration Rules

IEEE Access, 2020
Product integration (PI) rules are well known numerical techniques that are used to solve differential equations of integer and, recently, fractional orders. Due to the high memory dependency of the PI rules used in solving fractional-order systems (FOS),
Amr M. Abdelaty, Merna Roshdy, Lobna A. Said, Ahmed G. Radwan   +3 more
doaj   +1 more source

GRAph Parallel Actor Language: A Programming Language for Parallel Graph Algorithms [PDF]

, 2013
We introduce a domain-specific language, GRAph Parallel Actor Language, that enables parallel graph algorithms to be written in a natural, high-level form.
DeLorimier, Michael John
core   +1 more source

A framework for FPGA functional units in high performance computing [PDF]

, 2010
FPGAs make it practical to speed up a program by defining hardware functional units that perform calculations faster than can be achieved in software. Specialised digital circuits avoid the overhead of executing sequences of instructions, and they make
O'Donnell, J.T., Andreas Koltes, John T. O'Donnell, Koltes, A.   +3 more
core   +1 more source

Low Power QC-LDPC Decoder Based on Token Ring Architecture

Energies, 2020
The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption.
Mateusz Kuc, Wojciech Sułek, Dariusz Kania   +2 more
doaj   +1 more source

SIFO: Secure Computational Infrastructure Using FPGA Overlays

International Journal of Reconfigurable Computing, 2019
Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost.
Xin Fang, Stratis Ioannidis, Miriam Leeser   +2 more
doaj   +1 more source

FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels [PDF]

, 2012
Using FPGAs as hardware accelerators that communicate with a central CPU is becoming a common practice in the embedded design world but there is no standard methodology and toolset to facilitate this path yet.
I. Papaefstathiou, L. Lavagno, Παπαευσταθιου Ιωαννης(http://users.isc.tuc.gr/~ipapaefstathiou), Lavagno, Luciano, I. Mavroidis, Papaefstathiou Ioannis(http://users.isc.tuc.gr/~ipapaefstathiou), E. de la Torre, Papaefstathiou, I., F. Schafer, Papaefstathiou I., Schafer F., de la Torre E., Lazarescu, Mihai Teodor, Mavroidis I., M. Lazarescu, Papaefstathiou I., Lavagno L., De La Torre, E., Schafer, F., Mavroidis, I., Lazarescu M.   +20 more
core   +1 more source

FPGA Implementation of a General Space Vector Approach on a 6-Leg Voltage Source Inverter [PDF]

, 2011
A general algorithm of a Space Vector approach is implemented on a 6-leg VSI controlling a PM synchronous machine with three independent phases. In this last case, the necessity of controlling the zero-sequence current motivates the choice of a special ...
COLAS, Frédéric, S. Cense, F. Colas, SANDULESCU, Paul, BRUYERE, Antoine, E. Semail, A. Bruyere, KESTELYN, Xavier, L. Idkhajine, P. Sandulescu, SEMAIL, Eric, CENSE, Sébastien, X. Kestelyn, IDKHAJINE, Lahoucine   +13 more
core   +1 more source

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications

IEEE Access, 2016
In wireless communication schemes, turbo codes facilitate near-capacity transmission throughputs by achieving reliable forward error correction. However, owing to the serial data dependencies imposed by the underlying logarithmic Bahl-Cocke-Jelinek-Raviv
An Li, Peter Hailes, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo   +4 more
doaj   +1 more source

High performance FPGA implementation of the mersenne twister [PDF]

, 2008
Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twister is presented. The proposed architecture has the smallest footprint of all
Shrutisagar Chandrasekaran, Amira, A, Chandrasekaran, S, Abbes Amira   +3 more
core   +1 more source

PGA HPC Implementation of Microtubule Brownian Dynamics Simulations

Труды Института системного программирования РАН, 2018
This paper presents high performance simulation of microtubule molecular dynamics implemented on Xilinx Virtex-7 FPGA using high level synthesis tool Vivado HLS.
Y. A. Rumyanstev, P. N. Zakharov, N. A. Abrashitova, A. V. Shmatok, V. O. Ryzhikh, N. B. Gudimchuk, F. I. Ataullakhanov   +6 more
doaj   +1 more source