Results 41 to 50 of about 35,500 (242)
Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing [PDF]
, 2010 In November 2007 NIST announced that it would organize the SHA-3 competition to select a new cryptographic hash function family by 2012. In the selection process, hardware performances of the candidates will play an important role.
Akın, Abdulkadir +6 more
core +2 more sources
Advanced Functional Materials, EarlyView.This study demonstrates that memristors can replace conventional 2T–1C driving circuits with simplified 1T–1 m architectures by exploiting resistance switching. With ultra‐low switching voltages (< ±0.2 V) and multi‐level resistance states, the memristors precisely control the current injected into organic light‐emitting diodes (OLEDs).
Dong Hyun Kim +6 more
wiley +1 more source
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
International Journal of Reconfigurable Computing, 2013 This paper presents an FPGA tech-mapping algorithm dedicated to security applications. The objective is to implement—on a full-custom asynchronous FPGA—secured functions that need to be robust against side-channel attacks (SCAs).
Taha Beyrouthy, Laurent Fesquet
doaj +1 more source
Advanced Materials, EarlyView.Triply‐twinned architected lattices transform deformation from bending to stretching of struts, delivering up to threefold increases in stiffness and strength across polymeric and metallic systems. High‐resolution synchrotron XCT and image‐based simulations reveal how meta‐grain architecture, defects, and AM build orientation govern failure pathways ...
David McArthur +7 more
wiley +1 more source
FPGA Implementation of Fuzzy Interpreted Petri Net
IEEE Access, 2020 The paper introduces new implementation methods of the fuzzy interpreted Petri net (FIPN) on FPGAs. The realization of FIPN is based on fast array multipliers and multipliers utilizing DSP blocks available on FPGA systems. The paper contains descriptions
Zbigniew Hajduk, Jolanta Wojtowicz
doaj +1 more source
FPGA Acceleration of a Composite Kernel SVM for Hyperspectral Image Classification
IEEE Access, 2023 Hyperspectral image classification is one of the most important techniques for analyzing hyperspectral image that have hundreds of spectrum luminance values of near-infrared to visible light.
Kento Tajiri, Tsutomu Maruyama
doaj +1 more source
Speech Recognition on an FPGA Using Discrete and Continuous Hidden Markov Models [PDF]
, 2002 Speech recognition is a computationally demanding task, particularly the stage which uses Viterbi decoding for converting pre-processed speech data into words or sub-word units.
Melnikoff, Stephen Jonathan +2 more
core
Efficient TV white space filter bank transceiver [PDF]
, 2012 Future devices operating in the TV white space (TVWS) spectrum will require to access different bands at different locations and times in order to avoid interference to incumbent users, requiring agility and sufficient spectral masks to satisfy ...
Crockett, Louise Helen +5 more
core +1 more source
Spatial‐Wavelength Multiplexing Error‐Controlled Photonic Analog Computing System
Advanced Science, EarlyView.A novel photonic integrated circuit prototype implementing the concept of general‐purpose analog computing and demonstrate its capability in radio frequency applications. The chip features a multichannel architecture and performs fully optical analog computation with frequency‐domain parallel processing. An FPGA‐based error‐correction algorithm aims to
Tao Zhu +15 more
wiley +1 more source
Methodology of deployment of dependable FPGA based artificial intelligence as a service
Радіоелектронні і комп'ютерні системиThe subject of study in this article is the models, methods, and principles of organization of entire lifecycle of Artificial Intelligence (AI) as a Service implemented with the use of Field Programmable Gate Array (FPGA). The purpose of this work is the
Artem Perepelitsyn
doaj +1 more source