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Teaching FPGA security

2013 International Conference on Field-Programmable Technology (FPT), 2013
Teaching FPGA security to electrical engineering students is new at graduate level. It requires a wide field of knowledge and a lot of time. This paper describes a compact course on FPGA security that is available to electrical engineering master's students at the Saint-Etienne Institute of Telecom, University of Lyon, France.
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Security in SRAM FPGAs

IEEE Design & Test of Computers, 2007
As FPGAs have grown larger and more complex, the value of the IP implemented in them has grown commensurately. Since SRAM FPGAs reload their programming data every time they are powered up, an adversary can potentially copy the program as it is being loaded.
openaire   +1 more source

Securing qr codes by rsa on fpga

2017 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2017
QR codes, intended for maximum accessibility are widely in use these days and can be scanned readily by mobile phones. Their ease of accessibility makes them vulnerable to attacks and tampering. Certain scenarios require a QR code to be accessed by a group of users only.
Priyanka Gupta 0002   +2 more
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Secure, Remote, Dynamic Reconfiguration of FPGAs

ACM Transactions on Reconfigurable Technology and Systems, 2014
With the widespread availability of broadband Internet, Field-Programmable Gate Arrays (FPGAs) can get remote updates in the field. This provides hardware and software updates, and enables issue solving and upgrade ability without device modification. In order to prevent an attacker from eavesdropping or manipulating the configuration data, security is
Jo Vliegen   +2 more
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Multi-tenant FPGA Security

Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
An emerging trend in the data center is the at-scale deployment of Field-Programmable Gate Arrays (FPGAs) which combine multi-gigabit and ultra-low latency workload acceleration with hardware-level reconfigurability. In particular, for applications such as Deep Learning where techniques and algorithms are rapidly changing, the inherent flexibility of ...
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Self-authenticating secure boot for FPGAs

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2018
Secure boot within an FPGA environment is traditionally implemented using hardwired embedded cryptographic primitives and NVM-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration ...
Goutham Pocklassery   +4 more
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Securing Boot of an Embedded Linux on FPGA

2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum, 2011
The growing complexity of embedded systems makes reconfiguration and embedded OSs (Operating Systems) more and more interesting. FPGAs (Field-Programmable Gate Arrays) are able to perform such a feature with success. With most of the FPGAs, the OS is stored into an external memory (usually Flash) and running on a processor embedded into the FPGA.
Devic, Florian   +2 more
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FPGA Bitstream Security: A Day in the Life

2019 IEEE International Test Conference (ITC), 2019
Security concerns for field-programmable gate array (FPGA) applications and hardware are evolving as FPGA designs grow in complexity, involve sophisticated intellectual properties (IPs), and pass through more entities in the design and implementation flow.
Adam Duncan   +4 more
openaire   +1 more source

Secure IP downloading for SRAM FPGAs

Microprocessors and Microsystems, 2007
Nowadays there is a growing number of systems based on FPGAs spread over wide areas. When these kind of systems are used, serious security problems may appear. The configuration data for these devices can be very sensitive information that has to be protected against piracy and reverse engineering.
Javier Castillo   +2 more
openaire   +1 more source

Lightweight Secure Processor Prototype on FPGA

2018 28th International Conference on Field Programmable Logic and Applications (FPL), 2018
Lightweight devices usually come with an additional cryptographic co-processor for enabling the secrecy, in contrast, the master processor is typically a commercial processor where the required protection mechanism is missing. In this paper, an on-going effort in secured architecture named S-RISC-V based on RISC-V core is introduced.
Yao Liu 0006, Ray C. C. Cheung, Hei Wong
openaire   +1 more source

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