Results 201 to 210 of about 13,807 (264)

A novel interleaved nonisolated high gain DC-DC boost converter based on voltage multiplier rectifier. [PDF]

Sci Rep
Hosseinpour M, Seifi E, Seifi A, Sajedi S.   +3 more
europepmc   +1 more source

Quantum-Inspired Fourier Transforms Based on Circuits. [PDF]

Adv Sci (Weinh)
Zhang H, Sun Y, Zhang X.
europepmc   +1 more source

Securing the U.S. nucleic acid synthesis industry: a case for safe-harbor information sharing. [PDF]

Front Bioeng Biotechnol
Seltzer MJ, Isenberg AR, Flegler A, Walburger DW, Downs ME, Dileo J.   +5 more
europepmc   +1 more source

Dual-sensor coherence-driven adaptive denoising (WF-VMD-DDCDO) for underwater target detection. [PDF]

Sci Rep
Qiu H, Yang P, Huang C, Cao D, Zhang L, Han Y, Li S, Liu C, Ouyang J.   +8 more
europepmc   +1 more source

National Estimates of Liberia's 2021 Unintended Pregnancy and Induced Abortion. [PDF]

Int J Womens Health
Ushie BA, Giorgio M, Juma K, Donzo VL, Philbin J, Lu L, Bankole A, Massaquoi Snr MBF, Ouedraogo R, Dunbar NK.   +9 more
europepmc   +1 more source

Design and testing of frequency-doubling microstrip antenna sensor for wireless monitoring of high temperatures. [PDF]

Microsyst Nanoeng
Dong H, Guo L, Zhen C, Dong T, Fu H, Tian X, Liang S, Feng R, Tan Q.   +8 more
europepmc   +1 more source

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A high-frequency decimal multiplier

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings., 2004
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decimal data. This paper presents an iterative decimal multiplier, which operates at high clock frequencies and scales well to large operand sizes. The multiplier uses a new decimal
Robert D. Kenney, Michael J. Schulte, Mark A. Erle   +2 more
openaire   +2 more sources

Programmable Digital Frequency Multiplier

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
A programmable digital frequency multiplier with wide multiplication factor range and low lock time is presented. A digital algorithm is used to generate output frequency and an inbuilt PVT compensation mechanism ensures good frequency stability if there is any change in voltage and temperature during circuit operation. The circuit has been designed in
Sanjay Kumar Wadhwa, Deeya Muhury, Krishna Thakur   +2 more
openaire   +1 more source

Frequency Multipliers—An Overview and A 10.5 GHz Frequency Multiplier on TFG Substrate

IETE Technical Review, 1992
Most microwave engineers picture a coaxial cavity as a bulky construction, difficult to design at microwave frequencies. This paper demonstrates that multipliers at microwave frequencies can be designed by using microstripline techniques with normally used Teflon Fibre Glass substrates.
D V Ramana, L Suvarna, V Sambasiva Rao, A Bhaskaranarayana, S Pal   +4 more
openaire   +1 more source