Results 11 to 20 of about 325,757 (287)
The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates
IEEE Access, 2021 The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family.
Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui
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Frontiers in Physics, 2022 In large-area dynamic imaging, an active pixel sensor (APS) is proposed. However, there is a trade-off between signal-to-noise ratio (SNR) and spatial resolution.
Yunfeng Hu +4 more
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Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory
Nanoscale Research Letters, 2022 Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (V GC,ST ...
Hyangwoo Kim +6 more
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Double gate operation of metal nanodot array based single electron device
Scientific Reports, 2022 Multidot single-electron devices (SEDs) can enable new types of computing technologies, such as those that are reconfigurable and reservoir-computing. A self-assembled metal nanodot array film that is attached to multiple gates is a candidate for use in ...
Takayuki Gyakushi +4 more
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A 1K-Gate GaAs Gate Array, 1984 1050-gate arrays have been successfully designed and fabricated. Chip size is 3.75×3.75 mm. A basic cell can be programmed as an E/D-type DCFL three-input NOR gate. Speed performance measured at 0.2-mW/gate power dissipation was as follows. Unloaded (fanout=1) propagation delay time was 100 ps/gate.
Y. Ikawa +7 more
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Multiple-Submicron Channel Array Gate-Recessed AlGaN/GaN Fin-MOSHEMTs
IEEE Journal of the Electron Devices Society, 2018 In this paper, the multiple-submicron channel array gate-recessed AlGaN/GaN fin-metal-oxide-semiconductor high-electron mobility transistors (fin-MOSHEMTs) were fabricated using the photoelectrochemical oxidation method, the photoelectrochemical etching ...
Ching-Ting Lee, Hung-Yin Juo
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Three-dimensional neuroelectronic interface for peripheral nerve stimulation and recording: realization steps and contacting technology [PDF]
, 1994 A three-dimensional array of microelectrodes for use in intraneural stimulation and recording is presented. The 128 electrodes are at the tips of silicon needles, which are electrically insulated from each other.
Frieswijk, T.A. +2 more
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An Integrated ISFET Sensor Array
Sensors, 2009 A monolithically integrated ISFET sensor array and interface circuit are described. A new high-density, low-power source-drain follower was developed for the sensor array.
Kazuo Nakazato
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Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array
IEEE Journal of the Electron Devices Society, 2019 An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (
Xiaole Cui +4 more
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Control electronics for a neuro-electronic interface implemented in a gate array [PDF]
, 1995 Presents a Gate Array for implementing electronic circuitry to control multi-electrode arrays, which consist of 128 microelectrodes.
Frieswijk, Theo A. +3 more
core +2 more sources