Results 211 to 220 of about 40,049 (263)
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Recursive Gate-Arrays

1988
Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
M. Sarrafzadeh, S. Maddila, C. Chiang
openaire   +1 more source

A subnanosecond 8K-gate CMOS/SOS gate array

IEEE Journal of Solid-State Circuits, 1984
An 8370-gate CMOS/SOS gate array has been developed using a Si-gate CMOS/SOS process with two-level metallization. The gate lengths of the transistors are 1.8 and 1.9 /spl mu/m for the n-channel and p-channel, respectively. Subnanosecond typical gate delay times have been obtained.
S. Tanaka   +5 more
openaire   +1 more source

Quantum gate arrays as coherent sums over classical logic gate arrays

Journal of Physics A: Mathematical and General, 1997
Summary: Quantum spin systems may provide physical realizations of quantum gate arrays. It is shown that certain natural unitary time evolution matrices for \(\text{spin-} {1\over 2}\) quantum spins, interpreted in this context as quantum gate arrays, can be represented as coherent sums, with appropriate phases, over classical logic gate arrays, in a ...
Nachtergaele, Bruno, Periwal, Vipul
openaire   +1 more source

A 9000-gate user-programmable gate array

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003
The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources ...
H.-C. Hsieh   +7 more
openaire   +1 more source

Gate array technology

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
It is noted that gate arrays have come of age in the 1980s and CMOS is the dominant technology. Major advances in manufacturing, architecture, and integrated CAD (computer-aided design) tools have allowed predictable delivery of circuits with 100000 used gates.
openaire   +1 more source

13000 gate ECL compatible GaAs gate array

1989 Proceedings of the IEEE Custom Integrated Circuits Conference, 1989
A 13000-gate ECL (emitter-couples logic)-compatible gate array implemented in a proprietary self-aligned gate enhanced/depletion GaAs MESFET technology is described. This device operates from a single 2-V power supply and contains 196 ECL-compatible I/O ports.
B. Larkins   +4 more
openaire   +1 more source

Automated gate array scaling

IEEE Journal of Solid-State Circuits, 1984
A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, L.A. Akers, D.W. Still
openaire   +1 more source

Field-Programmable Gate Array

2021
Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer.
openaire   +1 more source

CMOS Gate Array Design

Hybrid Circuits, 1988
Software tools are an essential part of any IC design system but there are dangers associated with the introduction of CAD systems. This paper attempts to lift the software cloak which, along with the ubiquitous workstation, tends to cover the finer points of CMOS design.
openaire   +1 more source

500 gates GaAs gate array

Extended Abstracts of the 1982 International Conference on Solid State Devices, 1982
N. TOYODA   +3 more
openaire   +1 more source

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