Results 221 to 230 of about 2,187,465 (282)
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International journal of circuit theory and applications, 2018
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in ...
M. Alçin +4 more
semanticscholar +1 more source
It is well observed that cryptographic applications have great challenges in guaranteeing high security as well as high throughput. Artificial neural network (ANN)–based chaotic true random number generator (TRNG) structure has not been unprecedented in ...
M. Alçin +4 more
semanticscholar +1 more source
Japanese Journal of Applied Physics, 1983
High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda +4 more
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High speed GaAs DCFL gate array consisting of 500 3-INPUT NOR gates, in which 2000 FETs are integrated, has been successfully fabricated by a Pt buried gate planar E/D process technology. Eleven different 15-stage ring oscillators were made on this gate array to investigate the dependence of gate performance on various loading conditions.
Nobuyuki Toyoda +4 more
openaire +2 more sources
Field-Programmable Gate Arrays
Communications of the ACM, 1999Field programmable gate arrays (FPGAs) are a flexible alternative to custom integrated circuits. They can implement both combinatorial and sequential logic of tens of thousands of gates. Historically, software has been considered "flexible" with hardware its rigid counterpart in system design.
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Optically reconfigurable gate array using a colored configuration.
Applied Optics, 2018This paper presents a proposal of an optically reconfigurable gate array using a colored configuration. The optically reconfigurable gate array consists of a very-large-scale integration (VLSI), a holographic memory, and four lasers with different ...
Takumi Fujimori, Minoru Watanabe
semanticscholar +1 more source
Superconducting Magnetic Field Programmable Gate Array
IEEE transactions on applied superconductivity, 2018Field-programmable gate arrays (FPGAs) provide a significantly cheaper solution for various applications in traditional semiconductor electronics. Single flux quantum (SFQ) technologies are developing rapidly and the availability of SFQ-specific FPGA ...
N. Katam, O. Mukhanov, Massoud Pedram
semanticscholar +1 more source
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1982
This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
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This paper will describe a gate array with a loaded propagation delay of 2ns per gate. The device employs 2μm rules, double metal layers, silicon gate technology and bent-gate patterns for a minimum chip area.
M. Asano +8 more
openaire +2 more sources
IEEE Journal of Solid-State Circuits, 1984
A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
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A method for converting integrated circuit personalizations from a technology providing one set of design rules to a technology with a different and smaller set of design rules is presented. An example showing a conversion to a new technology where the cell area was reduced by 59% and the speed was increased more than 4.0% is illustrated.
K.J. Reasoner, D.W. Still, L.A. Akers
openaire +3 more sources
A 9000-gate user-programmable gate array
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 2003The 900-gate XC3090 CMOS user-programmable gate array is the largest member of a family of devices based on a second-generation logic cell array (LCA) architecture. This architecture features three types of user-configurable elements: an interior array of logic blocks, a perimeter of input/output (I/O) blocks, and interconnection resources ...
R. Kanazawa +7 more
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, 2016
The design and field programmable gate array implementation of a single-input fuzzy (SIF) proportional–integral–derivative (PID) control scheme applied to DC–DC buck converters are presented.
Changyuan Chang +3 more
semanticscholar +1 more source
The design and field programmable gate array implementation of a single-input fuzzy (SIF) proportional–integral–derivative (PID) control scheme applied to DC–DC buck converters are presented.
Changyuan Chang +3 more
semanticscholar +1 more source
1988
Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
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Abstract : The authors propose a regular architecture, called recursive gate- arrays, suitable for circuits with modules of nonuniform size. A set of n (rectangular and L-shaped) modules can be placed in a recursive gate-array. The placement can be obtained in O(n log n) time. Keywords: VLSI layout placement, Knock-knee model.
Chiang, C., Maddila, S., Sarrafzadeh, M.
openaire +2 more sources