Results 21 to 30 of about 2,144,818 (365)
Multiple-Submicron Channel Array Gate-Recessed AlGaN/GaN Fin-MOSHEMTs
IEEE Journal of the Electron Devices Society, 2018 In this paper, the multiple-submicron channel array gate-recessed AlGaN/GaN fin-metal-oxide-semiconductor high-electron mobility transistors (fin-MOSHEMTs) were fabricated using the photoelectrochemical oxidation method, the photoelectrochemical etching ...
Ching-Ting Lee, Hung-Yin Juo
doaj +1 more source
Energies, 2019 The Field Programmable Gate Array (FPGA) represents a valid solution for the design of control systems for inverters adopted in many industry applications, because of both its high flexibility of use and its high-performance with respect to other types ...
G. Ala +6 more
semanticscholar +1 more source
International Journal of Engine Research, 2018 Homogeneous charge compression ignition has the potential to significantly reduce NO x emissions, while maintaining a high fuel efficiency. Homogeneous charge compression ignition is characterized by compression-induced autoignition of a lean homogeneous
David C. Gordon +7 more
semanticscholar +1 more source
Compact field programmable gate array-based pulse-sequencer and radio-frequency generator for experiments with trapped atoms. [PDF]
Review of Scientific Instruments, 2015 We present a compact field-programmable gate array (FPGA) based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms.
T. Pruttivarasin, H. Katori
semanticscholar +1 more source
Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array
IEEE Journal of the Electron Devices Society, 2019 An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (
Xiaole Cui +4 more
doaj +1 more source
Structural Control & Health Monitoring, 2018 The numerical substructure of a real‐time hybrid simulation (RTHS) has been considerably simplified through condensation methods to relieve the burden incurred by computation.
Y. Duan +4 more
semanticscholar +1 more source
An Integrated ISFET Sensor Array
Sensors, 2009 A monolithically integrated ISFET sensor array and interface circuit are described. A new high-density, low-power source-drain follower was developed for the sensor array.
Kazuo Nakazato
doaj +1 more source
Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing
Science, 2019 Ionic floating-gate memories Digital implementations of artificial neural networks perform many tasks, such as image recognition and language processing, but are too energy intensive for many applications.
E. Fuller +11 more
semanticscholar +1 more source
Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates
Nanomaterials, 2022 We present an array of 225 field-effect transistors (FETs), where each of them has a graphene monolayer channel grown on a 3-layer deposited stack of 22 nm control HfO2/5 nm Ge-HfO2 intermediate layer/8 nm tunnel HfO2/p-Si substrate.
Mircea Dragoman +5 more
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Control electronics for a neuro-electronic interface implemented in a gate array [PDF]
, 1995 Presents a Gate Array for implementing electronic circuitry to control multi-electrode arrays, which consist of 128 microelectrodes.
Frieswijk, Theo A. +3 more
core +2 more sources