Results 31 to 40 of about 1,050,120 (328)
Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer [PDF]
ACM Symposium on Cloud Computing, 2020 Designing hardware accelerators for deep neural networks (DNNs) has been much desired. Nonetheless, most of these existing accelerators are built for either convolutional neural networks (CNNs) or recurrent neural networks (RNNs).
Siyuan Lu +4 more
semanticscholar +1 more source
IET Computers & Digital Techniques, 2022 Many recent research efforts have exploited data sparsity for the acceleration of convolutional neural network (CNN) inferences. However, the effects of data transfer between main memory and the CNN accelerator have been largely overlooked. In this work,
Jisu Kwon, Joonho Kong, Arslan Munir
doaj +1 more source
Hardware-accelerated dynamic binary translation [PDF]
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017 Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms.
Rokicki, Simon +2 more
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Hardware Acceleration of Sparse Oblique Decision Trees for Edge Computing
Elektronika ir Elektrotechnika, 2019 This paper presents a hardware accelerator for sparse decision trees intended for FPGA applications. To the best of authors’ knowledge, this is the first accelerator of this type. Beside the hardware accelerator itself, a novel algorithm for induction of
Predrag Teodorovic +1 more
doaj +1 more source
Differentiable Neural Architecture, Mixed Precision and Accelerator Co-Search
IEEE Access, 2023 Quantization, effective Neural Network architecture, and efficient accelerator hardware are three important design paradigms to maximize accuracy and efficiency.
Krishna Teja Chitty-Venkata +4 more
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Reliability Analysis of a Spiking Neural Network Hardware Accelerator
Design, Automation and Test in Europe, 2022 Despite the parallelism and sparsity in neural network models, their transfer into hardware unavoidably makes them susceptible to hardware-level faults.
Theofilos Spyrou +5 more
semanticscholar +1 more source
Multi-engine packet classification hardware accelerator [PDF]
, 2009 As line rates increase, the task of designing high performance architectures with reduced power consumption for the processing of router traffic remains important. In this paper, we present a multi-engine packet classification hardware accelerator, which
Kennedy, Alan +3 more
core +1 more source
Resistive Neural Hardware Accelerators
Proceedings of the IEEE, 2023 Deep Neural Networks (DNNs), as a subset of Machine Learning (ML) techniques, entail that real-world data can be learned and that decisions can be made in real-time. However, their wide adoption is hindered by a number of software and hardware limitations. The existing general-purpose hardware platforms used to accelerate DNNs are facing new challenges
Kamilya Smagulova +4 more
openaire +3 more sources
JetStream: Graph Analytics on Streaming Data with Event-Driven Hardware Accelerator
Micro, 2021 Graph Processing is at the core of many critical emerging workloads operating on unstructured data, including social network analysis, bioinformatics, and many others.
Shafiur Rahman +3 more
semanticscholar +1 more source
A High-Performance Multimem SHA-256 Accelerator for Society 5.0
IEEE Access, 2021 The development of a low-cost high-performance secure hash algorithm (SHA)-256 accelerator has recently received extensive interest because SHA-256 is important in widespread applications, such as cryptocurrencies, data security, data integrity, and ...
Thi Hong Tran +2 more
doaj +1 more source