Results 41 to 50 of about 1,050,120 (328)
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description [PDF]
International Conference on Architectural Support for Programming Languages and Operating Systems, 2021 The emergence of machine learning, image and audio processing on edge devices has motivated research towards power-efficient custom hardware accelerators. Though FPGAs are an ideal target for custom accelerators, the difficulty of hardware design and the
Kingshuk Majumder, Uday Bondhugula
semanticscholar +1 more source
The GPU vs Phi Debate: Risk Analytics Using Many-Core Computing [PDF]
, 2015 The risk of reinsurance portfolios covering globally occurring natural catastrophes, such as earthquakes and hurricanes, is quantified by employing simulations.
Varghese, Blesson
core +3 more sources
Design of a BP neural network SoC based on domestic embedded CPU
Dianzi Jishu Yingyong, 2021 The paper designs a Back Propagation(BP)neural network system on chip(SoC) based on the domestic embedded Central Processing Unit(CPU) CK803S and its SoC design platform.
Xu Wenliang
doaj +1 more source
Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture
IEEE Access, 2022 This paper proposes an effective hardware accelerator for 2D $8\times 8$ discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture.
Zhiwei Zhou, Z. Pan
semanticscholar +1 more source
Quantifying the latency benefits of near-edge and in-network FPGA acceleration [PDF]
, 2020 Transmitting data to cloud datacenters in distributed IoT applications introduces significant communication latency, but is often the only feasible solution when source nodes are computationally limited. To address latency concerns, cloudlets, in-network
Andrew Putnam +9 more
core +1 more source
FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
International Journal of Reconfigurable Computing, 2020 The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
Yuzhi Zhou, Xi Jin, Tianqi Wang
doaj +1 more source
Adaptive embedded technologies: hardware acceleration [PDF]
, 2021 This thesis establishes the benefits of multi-architecture systems by using reconfigurable modules in conjunction with a case integration strategy to improve system performance. The modules and strategies discussed in this thesis provide opportunities to the improve system performance of processing units designed for the consumer market.
openaire +1 more source
An ultra low-power hardware accelerator for automatic speech recognition [PDF]
, 2016 Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at a high energy cost which is not affordable for the tiny power budget of mobile devices.
Arnau Montañés, José María +3 more
core +1 more source
USING ARTIFICIAL INTELLIGENCE ACCELERATORS TO TRAIN COMPUTER GAME CHARACTERS
Компютерні системи та інформаційні технології, 2021 A review of the literature has shown that today, given the complexity of computational processes and the high cost of these processes, the gaming computer industry needs to improve hardware and software to increase the efficiency and speed of ...
YELYZAVETA HNATCHUK +2 more
doaj +1 more source
Remote Sensing, 2021 In recent years, research in the space community has shown a growing interest in Artificial Intelligence (AI), mostly driven by systems miniaturization and commercial competition.
E. Rapuano +6 more
semanticscholar +1 more source