Results 231 to 240 of about 46,646 (266)

Real-time signal processing enabled by fused networks on a memristor-based system on a chip. [PDF]

Sci Adv
Wang Z, Song W, Wang T, Wang Z, Xu Y, Rao M, Cai F, Yin W, Chen MS, Ge N, Collins M, Bai K, Ganguli S, Page MR, Wu Q, Katehi L, Xia Q, Hu M, Yang JJ.   +18 more
europepmc   +1 more source

Linear accelerator (linac) downtime analysis assisted with a Large Language Model (LLM). [PDF]

J Appl Clin Med Phys
Youn Y, Schulz JB, Stolen E, Farrey K, Muresan E, Kim S, Sohn JJ.   +6 more
europepmc   +1 more source

Development of a Fully Autonomous Offline Assistive System for Visually Impaired Individuals: A Privacy-First Approach. [PDF]

Sensors (Basel)
Mekonnen FY, Al Bataineh MF, Abu Abdoun D, Serag A, Tamiru KT, Abula W, Darota S.   +6 more
europepmc   +1 more source

A Hybrid Scale-Up and Scale-Out Approach for Performance and Energy Efficiency Optimization in Systolic Array Accelerators. [PDF]

Micromachines (Basel)
Sun H, Shen J, Zhang C, Liu H.
europepmc   +1 more source

Layer ensemble averaging for fault tolerance in memristive neural networks. [PDF]

Nat Commun
Yousuf O, Hoskins BD, Ramu K, Fream M, Borders WA, Madhavan A, Daniels MW, Dienstfrey A, McClelland JJ, Lueker-Boden M, Adam GC.   +10 more
europepmc   +1 more source

Some of the next articles are maybe not open access.

Related searches:

Hardware Accelerated Voxelisation

Computers & Graphics, 2000
Abstract This paper presents a hardware accelerated approach to the voxelization of a wide range of 3D objects, including curves/surfaces, solids, and volumetric CSG models. It allows 3D scenes to be modeled and manipulated in their own representations, and generates the volume representations of regions of interest on-the-fly for volumetric ...
Shiaofen Fang, Hongsheng Chen
openaire   +1 more source

Hardware Accelerated Data Analysis

Parallel Computing in Electrical Engineering, International Conference on, 2004
In this paper we present a massively parallel hardware accelerator for neural network based data mining applications. We use Self-Organizing Maps (SOM) for the analysis of very large datasets. One example is the analysis of semiconductor fabrication process data, which demands very high performance in order to achieve acceptable simulation times.
Franzmeier, M., Pohl, C., Porrmann, Mario, Rückert, Ulrich, ARRAY(0x919d200)   +4 more
openaire   +1 more source

Multimedia Execution Hardware Accelerator

Journal of VLSI signal processing systems for signal, image and video technology, 2001
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Hakkennes, Edwin, Vassiliadis, Stamatis
openaire   +2 more sources

Hybrid binary-unary hardware accelerator

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Stream-based computing such as stochastic computing has been used in recent years to create designs with significantly smaller area by harnessing unary encoding of data. However, the area saving comes at an exponential price in latency, making the area × delay cost unattractive.
S. Rasoul Faraji, Kia Bazargan
openaire   +1 more source

FFT hardware accelerator

IEEE Region 5 Conference, 1988: 'Spanning the Peaks of Electrotechnology', 2003
A novel signal processing architecture is described that performs the fast Fourier transform (FFT) in near-optimum time, with minimal hardware. State-of-the-art circuitry and careful layout support ultrafast operations. The processor is capable of executing several signal processing algorithms utilizing a microprogrammable control unit.
openaire   +1 more source