Results 1 to 10 of about 100,766 (255)

Digital Image Decoder for Efficient Hardware Implementation [PDF]

Sensors, 2022
Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression.
Goran Savić, Milan Prokin, Vladimir Rajović, Dragana Prokin   +3 more
doaj   +2 more sources

Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis [PDF]

Sensors, 2020
In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding ...
Riccardo Peloso, Maurizio Capra, Luigi Sole, Massimo Ruo Roch, Guido Masera, Maurizio Martina   +5 more
doaj   +2 more sources

Hardware implementation of memristor-based artificial neural networks [PDF]

Nature Communications
Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel.
Fernando Aguirre, Abu Sebastian, Manuel Le Gallo, Wenhao Song, Tong Wang, J. Joshua Yang, Wei Lu, Meng-Fan Chang, Daniele Ielmini, Yuchao Yang, Adnan Mehonic, Anthony Kenyon, Marco A. Villena, Juan B. Roldán, Yuting Wu, Hung-Hsi Hsu, Nagarajan Raghavan, Jordi Suñé, Enrique Miranda, Ahmed Eltawil, Gianluca Setti, Kamilya Smagulova, Khaled N. Salama, Olga Krestinskaya, Xiaobing Yan, Kah-Wee Ang, Samarth Jain, Sifan Li, Osamah Alharbi, Sebastian Pazos, Mario Lanza   +30 more
doaj   +2 more sources

Compressive Sensing Image Sensors-Hardware Implementation [PDF]

Sensors, 2013
The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image ...
Shahram Shirani, M. Jamal Deen, Mohammadreza Dadkhah   +2 more
doaj   +2 more sources

Hardware Implementation for Triaxial Contact-Force Estimation from Stress Tactile Sensor Arrays: An Efficient Design Approach [PDF]

Sensors
This paper presents a contribution to the state of the art in the design of tactile sensing algorithms that take advantage of the characteristics of generalized sparse matrix-vector multiplication to reduce the area, power consumption, and data storage ...
María-Luisa Pinto-Salamanca, Wilson-Javier Pérez-Holguín, José A. Hidalgo-López   +2 more
doaj   +2 more sources

Efficient Hardware Implementation of the LEDAcrypt Decoder

IEEE Access, 2021
This work describes an efficient implementation of the iterative decoder that is the main part of the decryption stage in the LEDAcrypt cryptosystem, recently proposed for post-quantum cryptography based on low-density parity-check (LDPC) codes.
Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina, Guido Masera   +5 more
doaj   +5 more sources

TinyJAMBU Hardware Implementation for Low Power

IEEE Access
In this paper, we present hardware implementations of the lightweight TinyJAMBU cipher with reduced power consumption using a mechanism based on shift register parallelization.
Carlos Fernandez-Garcia, J. M. Mora-Gutierrez, Carlos J. Jimenez-Fernandez   +2 more
doaj   +4 more sources

Intravenous glucose tolerance test hardware implementation [PDF]

Bulletin of the Polish Academy of Sciences: Technical Sciences, 2020
Blood glucose level monitoring and control is of utmost importance to millions of people who have been diagnosed with diabetes or similar illnesses.
D. Kulakovskis, T. Sledevič, A. Gedminas, D. Navakauskas   +3 more
doaj   +1 more source

Real-time fast learning hardware implementation

International Journal for Simulation and Multidisciplinary Design Optimization, 2023
Machine learning algorithms are widely used in many intelligent applications and cloud services. Currently, the hottest topic in this field is Deep Learning represented often by neural network structures.
Zhang Ming Jun, Garcia Samuel, Terre Michel   +2 more
doaj   +1 more source

Hardware implementation of the GPS authentication [PDF]

2012 International Conference on Reconfigurable Computing and FPGAs, 2012
In this paper, we explore new area/throughput trade- offs for the Girault, Poupard and Stern authentication protocol (GPS). This authentication protocol was selected in the NESSIE competition and is even part of the standard ISO/IEC 9798. The originality of our work comes from the fact that we exploit a fixed key to increase the throughput. It leads us
Dardaillon, Mickaël, Lauradoux, Cédric, Risset, Tanguy   +2 more
openaire   +3 more sources