Digital Image Decoder for Efficient Hardware Implementation [PDF]
Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression.
Goran Savić +3 more
doaj +2 more sources
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis [PDF]
In the last years, the need for new efficient video compression methods grown rapidly as frame resolution has increased dramatically. The Joint Collaborative Team on Video Coding (JCT-VC) effort produced in 2013 the H.265/High Efficiency Video Coding ...
Riccardo Peloso +5 more
doaj +2 more sources
Hardware implementation of memristor-based artificial neural networks [PDF]
Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel.
Fernando Aguirre +30 more
doaj +2 more sources
Compressive Sensing Image Sensors-Hardware Implementation [PDF]
The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image ...
Shahram Shirani +2 more
doaj +2 more sources
Efficient Hardware Implementation of the LEDAcrypt Decoder
This work describes an efficient implementation of the iterative decoder that is the main part of the decryption stage in the LEDAcrypt cryptosystem, recently proposed for post-quantum cryptography based on low-density parity-check (LDPC) codes.
Kristjane Koleci +5 more
doaj +5 more sources
Hardware Implementation for Triaxial Contact-Force Estimation from Stress Tactile Sensor Arrays: An Efficient Design Approach [PDF]
This paper presents a contribution to the state of the art in the design of tactile sensing algorithms that take advantage of the characteristics of generalized sparse matrix-vector multiplication to reduce the area, power consumption, and data storage ...
María-Luisa Pinto-Salamanca +2 more
doaj +2 more sources
TinyJAMBU Hardware Implementation for Low Power
In this paper, we present hardware implementations of the lightweight TinyJAMBU cipher with reduced power consumption using a mechanism based on shift register parallelization.
Carlos Fernandez-Garcia +2 more
doaj +4 more sources
On-Body and Off-Body Communications: A Comparative Study Between Hardware and Simulations [PDF]
The IEEE 802.15.6 standard defines wireless body area networks (WBANs) for communication in, on, and around the human body. However, commercially available hardware platforms that support direct experimental validation of IEEE 802.15.6-oriented WBAN ...
Drishti Oza +3 more
doaj +2 more sources
Intravenous glucose tolerance test hardware implementation [PDF]
Blood glucose level monitoring and control is of utmost importance to millions of people who have been diagnosed with diabetes or similar illnesses.
D. Kulakovskis +3 more
doaj +1 more source
Real-time fast learning hardware implementation
Machine learning algorithms are widely used in many intelligent applications and cloud services. Currently, the hottest topic in this field is Deep Learning represented often by neural network structures.
Zhang Ming Jun +2 more
doaj +1 more source

