An implementation method of missile speed compensation with FPGA on high speed moving platform
Dianzi Jishu Yingyong, 2019 In view of real-time demand for speed compensation on high speed moving platform, an implementation method of missile speed compensation is proposed.
Hou Kaiqiang +3 more
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A High-Speed Low-Cost Hardware Implementation for Depth Estimation Using Disparity Fusion Method
IEEE Access, 2022 Depth estimation using stereo images can be achieved by calculating the disparity values between the left and the right images captured by two parallel cameras. Reconstructing depth information from 2D images is crucial in many applications, such as self-
You-Rong Chen +5 more
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Towards hardware acceleration of neuroevolution for multimedia processing applications on mobile devices [PDF]
, 2006 This paper addresses the problem of accelerating large artificial neural networks (ANN), whose topology and weights can evolve via the use of a genetic algorithm.
Daniel Larkin +6 more
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Vehicle Type, Color and Speed Detection Implementation by Integrating VGG Neural Network and YOLO algorithm utilizing Raspberry Pi Hardware [PDF]
Journal of Artificial Intelligence and Data Mining, 2022 Vehicle type recognition has been widely used in practical applications such as traffic control, unmanned vehicle control, road taxation, smuggling detection, and so on. In this paper, various techniques such as data augmentation and space filtering have
Mojtaba Nasehi +2 more
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Hardware Implementation of 3D-Bresenham’s Algorithm Using FPGA
Tikrit Journal of Engineering Sciences, 2013 Traditional 3D-Bresenham’s algorithm is efficient in generating lines on raster systems using only integer calculations. This algorithm is needed as a solution of hidden surface problem using depth-buffer method to calculate z value for each pixel, while
Basma Mohammed Kamal Younis +1 more
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Non-recursive max* operator with reduced implementation complexity for turbo decoding [PDF]
, 2012 In this study, the authors deal with the problem of how to effectively approximate the max?? operator when having n > 2 input values, with the aim of reducing implementation complexity of conventional Log-MAP turbo decoders.
P. T. Mathiopoulos +5 more
core +1 more source
Hardware implementation of smart antenna systems [PDF]
Advances in Radio Science, 2006 Smart antenna systems attract a lot attentions now and believably more in the future, as it can increase the capacity of mobile communication systems dramatically.
H. Wang, M. Glesner
doaj
Design and Control of Multicoil Active Magnetic Bearing System for High-Speed Application
Energies, 2023 In the rotating machinery sector, active magnetic bearing (AMB) has drawn great attention due to its benefits over the conventional bearing system. The high-speed technology is enhanced by AMBs, which also reduce maintenance costs and eliminate friction ...
Sukanta Debnath +4 more
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Hardware architecture for lossless image compression based on context-based modeling and arithmetic coding [PDF]
, 2007 In this paper we present a novel hardware architecture for context-based statistical lossless image compression, as part of a dynamically reconfigurable architecture for universal lossless compression.
Vitulli, Raffaele +3 more
core +1 more source
Frontiers in Neuroscience, 2023 Recent developments in artificial neural networks and their learning algorithms have enabled new research directions in computer vision, language modeling, and neuroscience. Among various neural network algorithms, spiking neural networks (SNNs) are well-
Sangwoo Hwang +7 more
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