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RISC-V Instruction Set Architecture Extensions: A Survey
IEEE Access, 2023 RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions.
Enfang Cui, Tianzheng Li, Qian Wei
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GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing [PDF]
Sensors, 2020 This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing.
Krzysztof Marcinek, Witold A. Pleskacz
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Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V [PDF]
Sensors, 2022 In recent decades, there has been an increasing number of studies on control flow integrity (CFI), particularly those implementing hardware-assisted CFI solutions that utilize a special instruction set extension.
Seonghwan Park +3 more
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Understanding evolutionary potential in virtual CPU instruction set architectures. [PDF]
PLoS ONE, 2013 We investigate fundamental decisions in the design of instruction set architectures for linear genetic programs that are used as both model systems in evolutionary biology and underlying solution representations in evolutionary computation.
David M Bryson, Charles Ofria
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Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computing [PDF]
Nature CommunicationsSpiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning.
Jens E. Pedersen +14 more
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A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set [PDF]
International Journal of Antennas and Propagation, 2012 We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set.
Dau-Chyrh Chang +4 more
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Journal of Low Power Electronics and Applications, 2022 In-memory computing (IMC) aims to solve the performance gap between CPU and memories introduced by the memory wall. However, it does not address the energy wall problem caused by data transfer over memory hierarchies.
Kévin Mambu +3 more
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Optimization of beam pointing algorithm based on PowerPC
Dianzi Jishu Yingyong, 2021 Based on PowerPC architecture, this paper proposes an optimization strategy of beam pointing algorithm, which is realized from the trigonometric function calculation optimization, floating point arithmetic optimization, loop nesting optimization, and ...
Lei Shulan, Wu Huixiang, Li Wenxue
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A Multi-One Instruction Set Computer for Microcontroller Applications
IEEE Access, 2021 This work presents a simple integer-only instruction set architecture and microarchitecture derived from One Instruction Set Computers (OISCs) and embedding multiple execution modes ( ${m}$ OISC), capable of running at a reasonable performance level to ...
Marco Crepaldi +2 more
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PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA
IEEE Access, 2023 Processing-in-memory (PIM) has attracted attention to overcome the memory bandwidth limitation, especially for computing memory-intensive DNN applications.
Won Jun Lee +3 more
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