Understanding evolutionary potential in virtual CPU instruction set architectures. [PDF]
PLoS ONE, 2013 We investigate fundamental decisions in the design of instruction set architectures for linear genetic programs that are used as both model systems in evolutionary biology and underlying solution representations in evolutionary computation.
David M Bryson, Charles Ofria
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RISC-V Instruction Set Architecture Extensions: A Survey
IEEE Access, 2023 RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions.
Enfang Cui, Tianzheng Li, Qian Wei
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Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography
Transactions on Cryptographic Hardware and Embedded Systems, 2021 Side-channel attacks can break mathematically secure cryptographic systems leading to a major concern in applied cryptography. While the cryptanalysis and security evaluation of Post-Quantum Cryptography (PQC) have already received an increasing research
Tim Fritzmann +6 more
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Quantum Instruction Set Design for Performance [PDF]
Physical Review Letters, 2023 2 figures in main text and 21 figures in Supplementary Materials. This manuscript subsumes version 1 with significant improvements such as experimental demonstration and materials ...
Cupjin Huang +12 more
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GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing [PDF]
Sensors, 2020 This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing.
Krzysztof Marcinek, Witold A. Pleskacz
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Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V [PDF]
Sensors, 2022 In recent decades, there has been an increasing number of studies on control flow integrity (CFI), particularly those implementing hardware-assisted CFI solutions that utilize a special instruction set extension.
Seonghwan Park +3 more
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The design of scalar AES Instruction Set Extensions for RISC-V
Transactions on Cryptographic Hardware and Embedded Systems, 2020 Secure, efficient execution of AES is an essential requirement on most computing platforms. Dedicated Instruction Set Extensions (ISEs) are often included for this purpose. RISC-V is a (relatively) new ISA that lacks such a standardized ISE.
Ben Marshall +4 more
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Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computing [PDF]
Nature CommunicationsSpiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning.
Jens E. Pedersen +14 more
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A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set [PDF]
International Journal of Antennas and Propagation, 2012 We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set.
Dau-Chyrh Chang +4 more
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SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems [PDF]
Micro, 2021 Simple graph algorithms such as PageRank have been the target of numerous hardware accelerators. Yet, there also exist much more complex graph mining algorithms for problems such as clustering or maximal clique listing.
Maciej Besta +16 more
semanticscholar +1 more source