Results 241 to 250 of about 5,665,825 (297)

Compilers for Leakage Power Reduction

ACM Transactions on Design Automation of Electronic Systems, 2006
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts indicate that architectures, compilers, and software can be optimized so as to reduce the switching power (also known as dynamic power) in microprocessors.
Yi-Ping You, Jenq Kuen Lee
exaly   +2 more sources

Sleepy Stack Reduction of Leakage Power

Lecture Notes in Computer Science, 2004
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design.
Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger   +2 more
exaly   +3 more sources

Leakage power

Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05, 2005
Leakage power is emerging as a key challenge in IC design. Leakage is increasingly exponentially with each technology generation and is expected to become the dominant part of total power. Device threshold voltage scaling, shrinking device dimensions, and larger circuit sizes are causing this dramatic increase in leakage.
D. Blaauw, null Anirudh Devgan, null Farid Najm   +2 more
openaire   +1 more source

Leakage power profiling and leakage power reduction using DFT hardware

29th VLSI Test Symposium, 2011
In a CMOS logic circuit, the leakage power dissipated depends on the state of the design. In this paper we propose a novel technique to use the Q-gating logic that are added to reduce power during shift to also reduce leakage power during functional standby mode of the circuit. First, we propose leakage-aware test (λ-test) vector generation that can be
Rajamani Sethuram, Karim Arabi, Mohamed H. Abu-Rahma   +2 more
openaire   +2 more sources

Leakage Power Contributor Modeling

IEEE Design & Test of Computers, 2012
Low-power or power-aware design is one of the greatest challenges facing the semiconductor industry. The fidelity of low power design is dependent on the accuracy of power modeling across a wide range of PVT values. This paper describes an alternative “power contributor”based approach to cell leakage characterization that exploits inherent separability
Nagu R. Dhanwada, David J. Hathaway, Jerry Frenkil, W. Rhett Davis, Harun Demircioglu   +4 more
openaire   +2 more sources

LEAKAGE POWER REDUCTION OF ASYNCHRONOUS PIPELINES

Journal of Circuits, Systems and Computers, 2011
With CMOS technology scaling, leakage power is expected to become a significant portion of the total power. A dual-threshold CMOS circuit, which has both high and low threshold transistors in a single chip, can be used to deal with the leakage problem in high performance applications.
Behnam Ghavami, Hossein Pedram, Arezoo Salarpour   +2 more
openaire   +2 more sources