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Prediction of leakage power under process uncertainties
ACM Transactions on Design Automation of Electronic Systems, 2007In this article, we present a method to analyze the total leakage current of a circuit under process variations, considering interdie and intradie variations as well as the effect of the spatial correlations of intradie variations. The approach considers both the subthreshold and gate tunneling leakage power, as well as their interactions. With process
Hongliang Chang, Sachin S. Sapatnekar
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Leakage power optimization in standard-cell designs
Proceedings of the 17th symposium on Integrated circuits and system design, 2004Leakage power consumption is a growing concern in integrated circuit design. Nanometer CMOS transistors are characterized by significant sub-threshold and gate leakage currents and feature size scaling is exacerbating this problem. In today's technologies (i.e., 90nm), sub-threshold leakage currents are still dominant with respect to gate currents ...
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Leakage Power: Challenges and Solutions
2003The steady down-scaling of CMOS device dimensions has been the main stimulus for the growth of microelectronics and the computer industry over the last three decades. Without down-scaling, the recent proliferation of mobile devices such as portable phones and personal computers, and the tremendous performance of workstations could not have been ...
Mohab Anis, Mohamed Elmasry
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Leakage power bounds in CMOS digital technologies
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002The estimation of maximum and minimum leakage consumption for nominal values of the processing parameters is addressed. Tight upper and lower bounds of both extremes are found. In addition, input vectors producing a consumption close to these extremes are obtained.
Antoni Ferré, Joan Figueras
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A Study on Impact of Leakage Current on Dynamic Power
2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now become comparable to the switching current. Traditionally, dynamic power and leakage power are computed separately.
Ashesh Rastogi +2 more
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Techniques for Leakage Power Reduction
2009This chapter contains sections titled: Introduction Transistor Leakage Current Components Circuit Subthreshold Leakage Current Leakage Control Techniques This chapter contains sections titled: Acknowledgments ...
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Process Variation and Leakage Power
2011Technology scaling improves the energy, performance, and area of the digital circuits. With further scaling into sub-45nm regime, we are moving toward very low supply (VDD) and threshold voltages (VT), smaller VDD/VT ratio, high leakage current, and large Process Variation (PV).
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Leakage Power Characterization Considering Process Variations
2006We present a novel technique to accurately describe the leakage power in CMOS nanometer Integrated Circuits (ICs) considering process variations. The model predicts a leakage power increment due to process variations with high accuracy. It is shown that leakage increases considerably as channel length variations become larger due to technology scaling.
José Luis Rosselló +3 more
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Leakage power estimation and minimization in VLSI circuits
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002In low-power design for circuits, people want to reduce the power supply voltage, and this requires the transistor threshold voltages to also be reduced to maintain throughput and noise margins. However. This increases the subthreshold leakage current in p and n MOSFETs, which begins to increase the overall power in large circuits.
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Post-synthesis leakage power minimization
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012Mohammad Rahman, Carl Sechen
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