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Leakage power analysis of a 90nm FPGA
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2004Reconfigurable architectures, including FPGAs, are promising solutions for managing increasing design complexity while achieving both performance and flexibility. To support reconfiguration, FPGAs use more transistors per function than fixed-logic solutions, resulting in higher leakage power consumption.
Tim Tuan, Bo-Cheng Lai
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Characterization of leakage power in CMOS technologies
1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), 2002A model to statistically characterize the leakage power of CMOS digital circuits is presented. Based on the subthreshold leakage characterization at transistor and cell level, the leakage power consumption of a standard cell circuit is obtained. Also, in order to estimate the leakage power variability for a fixed state, a model of variations due to ...
Antoni Ferré, Joan Figueras
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Innovative power gating for leakage reduction
2008 IEEE International Symposium on Circuits and Systems, 2008Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-F/A reduced power gating structure is proposed for better reduction of leakage currents, especially ...
Masud H. Chowdhury +2 more
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System-on-chip power management considering leakage power variations
Proceedings of the 44th annual conference on Design automation - DAC '07, 2007The power characteristics of System-on-chips (SoCs) in nanoscale technologies are significantly impacted by process variations, making it important to consider these effects during system-level power analysis and optimization. In this paper, we identify and address the problem of designing effective power management schemes in the presence of such ...
Saumya Chandra +3 more
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Power balanced circuits for leakage-power-attacks resilient design
2015 Science and Information Conference (SAI), 2015The continuous rise of static power consumption in modern CMOS technologies has led to the creation of a novel class of security attacks on cryptographic systems. The latter exploits the correlation between leakage current and the input patterns to infer the secret key; it is called leakage power analysis (LPA). The use power-balanced (m-of-n) logic is
Basel Halak +2 more
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Leakage power-aware clock skew scheduling
Proceedings of the 45th annual Design Automation Conference, 2008Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and ...
Min Ni, Seda Ogrenci Memik
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Correcting Power Leakage Equation for Improved Leakage Modeling and Detection
Journal of Water Resources Planning and Management, 2020AbstractFluid pressure influences leakage flow rate in water distribution pipe networks. Significant progress has been made in the use of pressure management techniques to control leakage.
A. M. Kabaasha +2 more
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Leakage power consumption in FPGAs: Thermal analysis
2012 International Symposium on Wireless Communication Systems (ISWCS), 2012Current power saving techniques have been focused on reducing the dynamic power consumption induced by switching activity in CMOS digital circuits. Among these techniques, we can cite the clock gating, dynamic voltage frequency scaling, adaptive voltage scaling, and multiple voltage thresholds. Recently, as transistors sizes decrease, the leakage power
Nafkha, Amor +3 more
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2014
This chapter is concerned with leakage power minimization techniques. As leakage power minimization techniques exploit the threshold voltage to minimize leakage power, the dependence of delay and leakage power on threshold voltage is discussed first. Various techniques for the fabrication of multiple threshold voltages are briefly discussed.
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This chapter is concerned with leakage power minimization techniques. As leakage power minimization techniques exploit the threshold voltage to minimize leakage power, the dependence of delay and leakage power on threshold voltage is discussed first. Various techniques for the fabrication of multiple threshold voltages are briefly discussed.
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Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage
2007 44th ACM/IEEE Design Automation Conference, 2007In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate).
Tao Li, Zhiping Yu
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