Results 111 to 120 of about 49,624 (163)
Some of the next articles are maybe not open access.
Logic synthesis for manufacturability
IEEE Design and Test of Computers, 2004Design optimization during synthesis is for area and/or performance while optimization for yield occurs at the layout level. To obtain abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis.
Alessandra Nardi +1 more
openaire +1 more source
Tetrahedron, 1981
Abstract The background for synthesis design logic is presented, followed by the development of a procedure aimed at assessing all and locating the best synthetic routes. The procedure has two stages, first a dissection of skeleton, then a generation of necessary functionality on it to afford successive construction reactions.
JAMES B. HENDRICKSON +2 more
openaire +1 more source
Abstract The background for synthesis design logic is presented, followed by the development of a procedure aimed at assessing all and locating the best synthetic routes. The procedure has two stages, first a dissection of skeleton, then a generation of necessary functionality on it to afford successive construction reactions.
JAMES B. HENDRICKSON +2 more
openaire +1 more source
Logic synthesis with constraints
Microprocessing and Microprogramming, 1988Abstract Recent work in logic synthesis [Bra83], [Bra87a], [Bra87b] has resulted in the development of efficient algorithms for organizing and optimizing networks of logic expressions. A number of synthesis systems based on these or similar algorithms have been devised [Bar86], [The87], [Bra86]. In these, logic synthesis is performed in two stages:
A. Fox, C. T. Spracklen, C. P. Jolly
openaire +1 more source
Logic synthesis for testability
Proceedings of the Sixth Great Lakes Symposium on VLSI, 1996This paper presents a multilevel logic synthesis method that achieves 100% single stuck-at fault testability. We assume any cell library composed of AND/OR gates. The Fixed Polarity Reed-Muller forms are used to build the initial design. Algebraic factorizations and redundancy removal are two major steps that are used in deriving the final circuit.
Chien-Chung Tsai +1 more
openaire +1 more source
The role of learning in logic synthesis
[Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence, 1990The goal of logic synthesis is to obtain high-quality designs from specifications. Current approaches to logic synthesis often trade off design quality for technology independence. In this paper, we present a model of logic synthesis that uses technology-specific design rules and extends rule-based search to functional decomposition and technology ...
James R. Kipps, Daniel D. Gajski
openaire +2 more sources
Digest of Papers. COMPCON Spring 89. Thirty-Fourth IEEE Computer Society International Conference: Intellectual Leverage, 2003
A description is given of Sun's experiences as an early user of the Synopsys tools and the results of some experiments evaluating and comparing commercial logic synthesis tools. The behavior of the algorithms is discussed along with areas where the tools could be improved. >
openaire +1 more source
A description is given of Sun's experiences as an early user of the Synopsys tools and the results of some experiments evaluating and comparing commercial logic synthesis tools. The behavior of the algorithms is discussed along with areas where the tools could be improved. >
openaire +1 more source
Technology adaption in logic synthesis
Proceedings of the 23rd ACM/IEEE conference on Design automation - DAC '86, 1986Systems which synthesize logic implementations from specifications have moved, under the pressure of production requirements, from Boolean minimizers to procedures attempting to satisfy a wider range of criteria. Gate or cell count, taken as a measure of area, continues to be a major factor in design acceptability, but timing constraints, testability ...
William H. Joyner Jr. +4 more
openaire +1 more source
Logic transformations for synchronous logic synthesis
Twenty-Third Annual Hawaii International Conference on System Sciences, 2002An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints.
G. De Micheli, R. Yip
openaire +1 more source
Proceedings of the seventeenth design automation conference on Design automation - DAC '80, 1980
Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization.
John A. Darringer, William H. Joyner Jr.
openaire +1 more source
Despite many attempts to generate hardware implementations automatically from functional specifications, the literature does not record any commercial success. Previous efforts have dealt primarily with technology-independent primitives and have emphasized circuit minimization.
John A. Darringer, William H. Joyner Jr.
openaire +1 more source
Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), 1999
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
Robert K. Brayton, Sunil P. Khatri
openaire +1 more source
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
Robert K. Brayton, Sunil P. Khatri
openaire +1 more source