Results 1 to 10 of about 23,501 (117)

Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC [PDF]

Sensors, 2020
A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and ...
Juyong Lee, Younggyun Oh, Sein Oh, Hyungil Chae   +3 more
doaj   +2 more sources

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability [PDF]

Sensors, 2015
An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy.
Ismail Cevik, Xiwei Huang, Hao Yu, Mei Yan, Suat U. Ay   +4 more
doaj   +2 more sources

Monolithic integration of p- and n-type doped 2D WSe2 for wafer-scale complementary logic circuits [PDF]

Nature Communications
Atomically thin two-dimensional (2D) semiconductors are promising candidates for next-generation electronics, which could effectively suppress short-channel effects and consequently reduce static power consumption.
Yan Hu, Shicheng Zeng, Yi Wang, Jinshu Zhang, Yuxuan Zhu, Zhejia Zhang, Xiangqi Dong, Qicheng Sun, Mingrui Ao, Xinlong Guo, Jieya Shang, Yuexi Wang, Chao Liu, Yuchen Tian, Haojie Chen, Xinliu He, Yufei Song, Yue Zhang, Sen Wang, Junlong Shi, Zhengjie Sun, Jiahao Wang, Jichao Li, Liping Jiang, Lin Wang, Chao Zhu, Zihan Xu, Saifei Gou, Yin Wang, Yin Xia, Xu Wang, Zhengzong Sun, Wenzhong Bao   +32 more
doaj   +2 more sources

A 2.03-mW CMOS Image Sensor With an Integrated Four-Stacked Charge-Recycling Driver for Image Signal Transmission

IEEE Access, 2022
We propose a CMOS image sensor with a dedicated low-power imaging mode and low-power integrated transmitter. The proposed CMOS image sensor selectively operates in dual mode: a high-quality mode with a 1.5 V supply voltage of readout circuits to achieve ...
Sang-Hoon Kim, Yongsung Cho, Jiwon Lee, Jung-Hoon Chun, Jaehyuk Choi   +4 more
doaj   +1 more source

SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology

IEEE Journal of the Electron Devices Society, 2022
Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices.
Tianshi Liu, Hua Zhang, Sundar Babu Isukapati, Emran Ashik, Adam J. Morgan, Bongmook Lee, Woongje Sung, Ayman Fayed, Marvin H. White, Anant K. Agarwal   +9 more
doaj   +1 more source

Low Power Clock Generator Design With CMOS Signaling

IEEE Open Journal of the Solid-State Circuits Society, 2021
The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more
Yongping Fan, Ian A. Young
doaj   +1 more source

Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2

iScience, 2021
Summary: Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low ...
Wanying Du, Xionghui Jia, Zhixuan Cheng, Wanjing Xu, Yanping Li, Lun Dai   +5 more
doaj   +1 more source

Low Noise Low Power CMOS Telescopic-OTA for Bio-Medical Applications

Computers, 2016
The preamplifier block is crucial in bio-medical signal processing. The power intensive Operational Transconductance Amplifier (OTA) is considered, and the performance of preamplifier is studied.
Bellamkonda Saidulu, Arun Manoharan, Kumaravel Sundaram   +2 more
doaj   +1 more source

Semidigital PLL Design for Low-Cost Low-Power Clock Generation

Journal of Electrical and Computer Engineering, 2011
This paper describes recent semidigital architectures of the phase-locked loop (PLL) systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC), the semi-digital PLL (SDPLL) enables low-power linear phase ...
Ni Xu, Woogeun Rhee, Zhihua Wang
doaj   +1 more source

Low power‐delay‐product dynamic CMOS circuit design techniques

Electronics Letters, 2017
Two low power‐delay‐product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP.
H. Xue, S. Ren
doaj   +1 more source