Results 11 to 20 of about 22,126 (267)
A Low Power Energy-Efficient Precision CMOS Temperature Sensor †
Micromachines, 2018 This paper presents a low power, energy-efficient precision CMOS temperature sensor. The front-end circuit is based on bipolar junction transistors, and employs a pre-bias circuit and bipolar core.
Rongshan Wei, Xiaotian Bao
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Journal of Low Power Electronics and Applications, 2011 Recently, double-gate MOSFETs (DGMOSFETs) have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS.
Tony T. Kim +3 more
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Low-Power CMOS Integrated Hall Switch Sensor
Active and Passive Electronic Components, 2017 This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit.
Rongshan Wei, Shizhong Guo, Shanzhi Yang
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Low-power-consumption CMOS inverter array based on CVD-grown p-MoTe2 and n-MoS2
iScience, 2021 Summary: Two-dimensional (2D) semi-conductive transition metal dichalcogenides (TMDCs) have shown advantages for logic application. Complementary metal-oxide-semiconductor (CMOS) inverter is an important component in integrated circuits in view of low ...
Wanying Du +5 more
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A low-power CMOS analog vector quantizer [PDF]
IEEE Journal of Solid-State Circuits, 1997 We present a parallel analog vector quantizer (VQ) in 2.0-/spl mu/m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16/spl times/16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell
Gert Cauwenberghs, Volnei A. Pedroni
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A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems
IEEE Journal of the Electron Devices Society, 2016 The reasons why state-of-the-art vertical bipolar circuits dissipate very high power are explained. The recent advent of SOI symmetric lateral bipolar transistors invites us to rethink bipolar as a high-speed but low-power technology.
Tak H. Ning
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The Optimal Wire Order for Low Power CMOS [PDF]
, 2005 If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program.
Paul Zuber +3 more
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Design and Simulation of Reversible Logic Gate Using HCS Macro-Model
Memories - Materials, Devices, Circuits and Systems—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc.
Snigdha Chowdhury Kolay +2 more
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A cryogenic low power CMOS analog buffer at 4.2K
IEICE Electronics Express, 2021 A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at ...
Yajie Huang +5 more
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Low Power Differential CMOS Schmitt Trigger with Adjustable Hysteresis
Advances in Electrical and Electronic Engineering, 2017 This paper proposes a novel differential CMOS Schmitt trigger with adjustable hysteresis. The hysteresis of the proposed circuit is generated using cross-coupled pMOS or nMOS transistors, which can be tuned by engineering cross-coupled transistors ...
Rachna Dhaval Jani, Shruti Oza
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