Results 21 to 30 of about 14,704,035 (301)
A low-power CMOS analog vector quantizer [PDF]
IEEE Journal of Solid-State Circuits, 1997 We present a parallel analog vector quantizer (VQ) in 2.0-/spl mu/m double-poly CMOS technology and analyze its energetic efficiency. The prototype chip contains an array of 16/spl times/16 charge-based distance estimation cells, implementing a 16 analog input, 4-b coded output VQ with a mean absolute difference (MAD) distance metric. The distance cell
Gert Cauwenberghs, Volnei A. Pedroni
openaire +1 more source
A Perspective on SOI Symmetric Lateral Bipolar Transistors for Ultra-Low-Power Systems
IEEE Journal of the Electron Devices Society, 2016 The reasons why state-of-the-art vertical bipolar circuits dissipate very high power are explained. The recent advent of SOI symmetric lateral bipolar transistors invites us to rethink bipolar as a high-speed but low-power technology.
Tak H. Ning
doaj +1 more source
Low power domino logic circuits in deep-submicron technology using CMOS
Engineering Science and Technology, an International Journal, 2018 Leakage power and propagation delay are the two major challenges in designing CMOS VLSI circuits, in deep sub-micron technology. This paper proposes a novel technique: Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic ...
Sandeep Garg, Tarun Kumar Gupta
doaj +1 more source
A Low Power Energy-Efficient Precision CMOS Temperature Sensor †
Micromachines, 2018 This paper presents a low power, energy-efficient precision CMOS temperature sensor. The front-end circuit is based on bipolar junction transistors, and employs a pre-bias circuit and bipolar core.
Rongshan Wei, Xiaotian Bao
doaj +1 more source
Low-Power CMOS Integrated Hall Switch Sensor
Active and Passive Electronic Components, 2017 This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit.
Rongshan Wei, Shizhong Guo, Shanzhi Yang
doaj +1 more source
The Optimal Wire Order for Low Power CMOS [PDF]
, 2005 If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program.
Paul Zuber +3 more
openaire +2 more sources
A cryogenic low power CMOS analog buffer at 4.2K
IEICE Electronics Express, 2021 A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18um CMOS technology show the high driving capability and low quiescent power consumption at ...
Yajie Huang +5 more
openaire +3 more sources
Design and Simulation of Reversible Logic Gate Using HCS Macro-Model
Memories - Materials, Devices, Circuits and Systems—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc.
Snigdha Chowdhury Kolay +2 more
doaj +1 more source
Design of Low-Power CMOS OTA Using Bulk-Drive Technique [PDF]
Journal of Intelligent Procedures in Electrical Technology, 2015 This paper presents the design of low power CMOS- OTA (operational transconductance amplifier) using bulk drive (BD) technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example ...
Maryam Ghadiri Modarres
doaj
Analysis of the subthreshold CMOS logic inverter
Ain Shams Engineering Journal, 2018 There is no doubt that operating the MOSFET transistor in the subthreshold region, where the power-supply voltage is less than the threshold voltage, has an increasing importance due to the reduced power consumption.
Sherif M. Sharroush
doaj +1 more source