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Proceedings of the Tenth International Conference on Microelectronics (Cat. No.98EX186), 2002
This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity).
A. Guyot, S. Abou-Samra
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This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity).
A. Guyot, S. Abou-Samra
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Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 2002
Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its ...
null Kei-Yong Khoo, A.N. Willson
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Modern high speed CMOS processors using on-chip phase-locked-loops often require a clock buffer with stringent specifications on the signal's rise time and fall time rather than on the buffer's delay time. For these applications, we propose a low power CMOS clock buffer that momentarily tri-states its output to minimize its power dissipation and its ...
null Kei-Yong Khoo, A.N. Willson
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Ultra-low-power CMOS technologies
1996 International Semiconductor Conference. 19th Edition. CAS'96 Proceedings, 2002The fast growing portable-electronics market as well as thermal dissipation, reliability, and scalability issues have launched a massive trend towards low-power and low-voltage technologies. This has lead to a new, reduced standard digital CMOS supply voltage of 3.3 V reducing the power consumption by 70%.
G. Schrom, S. Selberherr
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[1991] Proceedings. First Great Lakes Symposium on VLSI, 2002
A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable.
J. Canaris, S. Whitaker
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A full custom, 25 MHz, 1.6 mu m CMOS correlator chip is presented. The 5.15 mm by 4.23 mm chip performs either autocorrelation or crosscorrelation, consuming less than 10 mW per channel. The correlator, designed for a space borne spectrometer, contains 32 channels and is cascadable.
J. Canaris, S. Whitaker
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1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268), 2002
Low power design is the key for wireless communication devices and portable computing systems. Many logic families are suggested as candidates for low power design. In this paper we compare four famous logic families as candidates for low power and high performance logic circuits. The comparisons are based on power delay and interference produced. A 16
M.W. Adam, M.I. Elmasry
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Low power design is the key for wireless communication devices and portable computing systems. Many logic families are suggested as candidates for low power design. In this paper we compare four famous logic families as candidates for low power and high performance logic circuits. The comparisons are based on power delay and interference produced. A 16
M.W. Adam, M.I. Elmasry
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International Journal of High Speed Electronics and Systems, 1994
A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS.
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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS.
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1998
From the Publisher: This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.
Anantha Chandrakasan +1 more
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From the Publisher: This collection of important papers provides a comprehensive overview of low-power system design, from component technologies and circuits to architecture, system design, and CAD techniques. LOW POWER CMOS DESIGN summarizes the key low-power contributions through papers written by experts in this evolving field.
Anantha Chandrakasan +1 more
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Cryogenic ultra low power CMOS
1995 IEEE Symposium on Low Power Electronics. Digest of Technical Papers, 2002This paper reports 7-stage 1.5 /spl mu/m zeroVt CMOS ring oscillators operating at 170 MHz/V down to V/sub dd/=70 mV at room temperature, and 360 MHz/V down to V/sub dd/=27 mV at 77 K.
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Proceedings of the 39th conference on Design automation - DAC '02, 2002
An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low ...
Michiel Steyaert, Peter Vancorenland
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An overview and comparison of different topologies for wireless architectures are discussed, where the main focus lies on the power consumption and possibilities towards integration and reduction of external components. Architectures with reduced number of building blocks (both internal and external) are presented where the main benefits are the low ...
Michiel Steyaert, Peter Vancorenland
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Low-power CMOS continuous-time filters
IEEE Journal of Solid-State Circuits, 1996A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance.
R.H. Zele, D.J. Allstot
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