Results 231 to 240 of about 14,986,572 (302)

Non-linear pyroelectric energy harvesting with commercial multilayer capacitors.

J Mater Chem A Mater
Helt A, Ramírez O, El Moul A, Valle N, Bamberg C, Defay E.   +5 more
europepmc   +1 more source

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Low-voltage low-power LVDS drivers

IEEE Journal of Solid-State Circuits, 2005
Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications.
Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson   +3 more
openaire   +2 more sources

Low voltage, low power operational amplifier

10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2004
A 0.8 V folded cascode operational amplifier was designed in 0.18-/spl mu/m standard CMOS technology. Emphasis was placed on observing the low voltage design and using current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing threshold voltage.
Shahab Ardalan, Kaamran Raahemifar, Fei Yuan 0005   +2 more
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A low-voltage, low-power CMOS delay element

IEEE Journal of Solid-State Circuits, 1996
A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current.
Gyudong Kim, Min-Kyu Kim, Byoung-Soo Chang, Wonchan Kim   +3 more
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A low — Voltage hysteresis comparator for low power applications

2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017
A Hysteresis comparator with low supply voltage is proposed. The comparator has PMOS input stage, NMOS current mirror, and PMOS load stage using positive feedback. The signal of the PMOS input stage is sent to the PMOS load stage via the NMOS current mirror. Positive feedback of the PMOS load stage introduces bistable characteristics to the comparator.
Takumi Saito, Satoshi Komatsu
openaire   +2 more sources