Results 231 to 240 of about 12,837,062 (300)
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Low voltage, low power operational amplifier
10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003, 2004A 0.8 V folded cascode operational amplifier was designed in 0.18-/spl mu/m standard CMOS technology. Emphasis was placed on observing the low voltage design and using current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing threshold voltage.
Shahab Ardalan +2 more
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Low-voltage low-power LVDS drivers
IEEE Journal of Solid-State Circuits, 2005Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications.
Mingdeng Chen +3 more
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A low-voltage, low-power CMOS delay element
IEEE Journal of Solid-State Circuits, 1996A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current.
Gyudong Kim +3 more
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Low voltage swing gates for low power consumption
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003A low swing voltage design technique is proposed. The new design could be used successfully in order to decrease the power dissipation in Complementary Pass-Transistor Logic (CPL) as in Cascade Voltage Switch Logic (CVSL) logic gates. The achieved gate output voltage-level swing reduction, results in a significant reduction of their power consumption ...
Abdoul Rjoub, Odysseas G. Koufopavlou
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A low voltage low power CMOS analog multiplier
2011 NORCHIP, 2011This paper presents a single low-voltage CMOS analog multiplier with low-power consumption. It consists of four voltage adders and a multiplier core. The proposed circuit is simulated with HSPICE and simulation results have shown that, under single 0.9V supply voltage, the circuit has smaller than 1.8% linearity error and 0.88% THD under the maximum ...
Amir H. Miremadi +2 more
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