Results 31 to 40 of about 370 (180)
Analysis and Optimization of MPSoC Reliability
Journal of Low Power Electronics, 2006 Advancements in technology enable integration of multiple devices on a single core, resulting in increased on chip power and temperature densities. Higher temperatures, in turn, present a significant challenge for reliability. In this work we propose a comprehensive framework for analyzing reliability of multi-core systems, considering permanent faults.
Ayse Kivilcim Coskun +4 more
openaire +2 more sources
Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs
IEEE Access, 2020 This paper presents a run-time solver for the inverse kinematics of a robotic arm implemented on a heterogeneous Multi-Processor System-on-Chip (MPSoC).
Leonardo Suriano +4 more
doaj +1 more source
CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems
Future Internet, 2022 Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance requirements and reduce power consumption when executing an application.
Somdip Dey +4 more
doaj +1 more source
Accelerating m‐Invariance for Continuous Big Data Publishing
IEEJ Transactions on Electrical and Electronic Engineering, Volume 21, Issue 4, Page 568-579, April 2026.To prevent personal information leakage from the collection and publication of big data, anonymization techniques that protect privacy while preserving data utility are essential. In particular, m‐invariance provides privacy protection for dynamic datasets that are continuously published as records are updated.
Kentaro Morise, Hiroaki Nishi
wiley +1 more source
Applied Sciences, 2023 Algorithms and computing power have consistently been the two driving forces behind the development of artificial intelligence. The computational power of a platform has a significant impact on the implementation cost, performance, power consumption, and
Tianling Li, Bin He, Yangyang Zheng
doaj +1 more source
Optimized Hybrid Deep Learning‐Based FPGA Accelerators for Denoising of Ultrasound Breast Images
IET Circuits, Devices &Systems, Volume 2026, Issue 1, 2026.This paper introduces a novel image‐denoising technique that integrates a hybrid deep learning (DL) model with a self‐improved orca predation (SOP) strategy. This hybrid model improves denoising performance by integrating a Convolutional Neural Network (CNN) with Bidirectional Long Short‐Term Memory (Bi‐LSTM).
K. Janaki +4 more
wiley +1 more source
Reducing the Energy Footprint of 5G: A gNB on MPSoC With Low-Power FFT Acceleration
IEEE Open Journal of the Communications SocietyOpen, virtualized architectures are reshaping cellular networks, but purely software-based 5G deployments often struggle to meet strict real-time requirements.
Abdelghani Bourenane +3 more
doaj +1 more source
Systems, 2017 Approaches for the design of fault tolerant Network-on-Chip (NoC) for use in System-on-Chip (SoC) reconfigurable technology using Field-Programmable Gate Array (FPGA) technology are challenging, especially in Multiprocessor System-on-Chip (MPSoC) design.
Hayat Daoud +4 more
doaj +1 more source
Computation, 2020 New challenges in Astronomy and Astrophysics (AA) are urging the need for many exceptionally computationally intensive simulations. “Exascale” (and beyond) computational facilities are mandatory to address the size of theoretical problems and data coming
David Goz +9 more
doaj +1 more source
Fault injection and failure analysis on Xilinx 16 nm FinFET Ultrascale+ MPSoC
Nuclear Engineering and Technology, 2022 Energetic particle strikes the device and induces data corruption in the configuration memory (CRAM), causing errors and even malfunctions in a system on chip (SoC). Software-based fault injection is a convenient way to assess device performance. In this
Weitao Yang, Yonghong Li, Chaohui He
doaj +1 more source