Results 41 to 50 of about 370 (180)

FPGA‐Based Dual Path ConvNeXt‐Tiny–ViT With Effective Feature Refinement for Skin Cancer Classification

IET Computers &Digital Techniques, Volume 2026, Issue 1, 2026.
Skin cancer is the dangerous life‐threatening disease and is increasing rapidly due to environmental changes and lifestyle factors. The treatment for skin cancer is possible if detected at an early stage, but if not detected early, the possibility of successful treatment is reduced.
Jamel Smida, Mohamed Karim Azizi, Anandh Sam Chandra Bose, Amor Smida, Srinivas Katkoori   +4 more
wiley   +1 more source

Towards a Component-Based Observation of MPSoC [PDF]

2009 International Conference on Parallel Processing Workshops, 2009
In this document, we propose a component-based approach to provide a well-suited solution to the programming and deployment problems of systems on chip (SoC) that can become increasingly complex and heterogeneous. Focusing on the aspect of observation, we show, from system to application, that components help in observing all software levels.
Prada Rojas, Carlos Hernan, Marangonzova-Martin, Vania, Georviev, Kiril, Méhaut, Jean-François, Santana, Miguel   +4 more
openaire   +3 more sources

UASR‐A: An Efficient Edge Super‐Resolution Accelerator With Hardware‐Algorithm Co‐Design Techniques

Electronics Letters, Volume 62, Issue 1, January/December 2026.
Deploying high‐performance super‐resolution on resource‐constrained edge devices is difficult due to heavy computation and memory bandwidth limits. We propose a hardware software co‐design consisting of a lightweight unified‐attention super‐resolution network (UASR) network (ConvFormer with unified‐attention mixer [UA‐M] and reparameterized edge ...
Yuqiao Huang, Dihu Chen, Tao Su
wiley   +1 more source

Hardware Accelerators for Elliptic Curve Cryptography [PDF]

Advances in Radio Science, 2008
In this paper we explore different hardware accelerators for cryptography based on elliptic curves. Furthermore, we present a hierarchical multiprocessor system-on-chip (MPSoC) platform that can be used for fast integration and evaluation of novel ...
C. Puttmann, J. Shokrollahi, M. Porrmann, U. Rückert   +3 more
doaj  

Utility‐Aware Scheduling of Sensor Update Transactions on Multiprocessor Platforms

Journal of Sensors, Volume 2026, Issue 1, 2026.
Scheduling sensor update transactions to maintain data temporal validity has been recognized as an important problem in cyber‐physical system research. Previous work focuses on minimizing the update workload produced by transactions. In this paper, we study the problem of scheduling a set of sensor update transactions on multiprocessor platforms to ...
Tian Bai, Bo Fan, Hua Dai, Pramita Mishra   +3 more
wiley   +1 more source

A neuromorphic system based on spiking‐timing‐dependent plasticity for evaluating wakefulness and anesthesia states using intracranial EEG signals

VIEW, Volume 6, Issue 4, August 2025.
Existing clinical approaches for assessing anesthesia depth often rely on physiological and behavioral indicators, which can be unreliable due to uncertain correlation with patient consciousness. This study presents a neuromorphic SNN with STDP, implemented on an field‐programmable gate array (FPGA) platform, enabling real‐time iEEG‐based assessment of
Ke Chen, Zehan Wu, Yuhao Xu, Ruijing Wang, Shize Jiang, Liang Chen, Fang Zhao, Ying Mao, Meng Li   +8 more
wiley   +1 more source

Scheduling the Exchange of Context Information for Time-Triggered Adaptive Systems

Algorithms
This paper presents a novel metascheduling algorithm to enhance communication efficiency in off-chip time-triggered multi-processor system-on-chip (MPSoC) platforms, particularly for safety-critical applications in aerospace and automotive domains.
Daniel Onwuchekwa, Omar Hekal, Roman Obermaisser   +2 more
doaj   +1 more source

Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates

International Journal of Reconfigurable Computing, 2011
The aggressive scaling of CMOS technology has increased the density and allowed the integration of multiple processors into a single chip. Although solutions based on MPSoC architectures can increase application's speed through TLP exploitation, this ...
Monica Magalhães Pereira, Luigi Carro
doaj   +1 more source

EthVault: A Secure and Resource‐Conscious FPGA‐Based Ethereum Cold Wallet

IET Blockchain, Volume 5, Issue 1, January/December 2025.
This work presents EthVault, the first hardware‐based Ethereum hierarchical deterministic cold wallet, featuring FPGA implementations of key cryptographic algorithms for secure key generation. A novel ECC architecture resilient to side‐channel and timing attacks, along with an efficient child key derivation function, are introduced. Implementation on a
Joel Poncha Lemayian, Ghyslain Gagnon, Kaiwen Zhang, Pascal Giard   +3 more
wiley   +1 more source

Efficient Edge-AI Application Deployment for FPGAs

Information, 2022
Field Programmable Gate Array (FPGA) accelerators have been widely adopted for artificial intelligence (AI) applications on edge devices (Edge-AI) utilizing Deep Neural Networks (DNN) architectures.
Stavros Kalapothas, Georgios Flamis, Paris Kitsos   +2 more
doaj   +1 more source