Results 11 to 20 of about 4,133,040 (316)
Identification of Multi-Core Interference [PDF]
2019 IEEE 19th International Symposium on High Assurance Systems Engineering (HASE), 2019 The CAST-32A provides some guidelines to help certify multi-core-based systems in the avionics domain. One major requirement is to compute all the potential interference and to provide adequate mitigation means. In this paper, we compare two approaches to identify the interference: the initiator-target and the Phylog models.
Frédéric Boniol +2 more
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Multi-core Symbolic Bisimulation Minimisation [PDF]
International Journal on Software Tools for Technology Transfer, 2016 We introduce parallel symbolic algorithms for bisimulation minimisation, to combat the combinatorial state space explosion along three different paths. Bisimulation minimisation reduces a transition system to the smallest system with equivalent behaviour.
Tom van Dijk, Jaco van de Pol
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A Flexible Heterogeneous Multi-Core Architecture [PDF]
16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007 Peer ...
Pericàs Gleim, Miquel +5 more
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Multi-core On-The-Fly Saturation [PDF]
, 2019 Saturation is an efficient exploration order for computing the set of reachable states symbolically. Attempts to parallelize saturation have so far resulted in limited speedup. We demonstrate for the first time that on-the-fly symbolic saturation can be successfully parallelized at a large scale. To this end, we implemented saturation in Sylvan’s multi-
Dijk, Tom van +2 more
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Neural Simulations on Multi-Core Architectures [PDF]
Frontiers in Neuroinformatics, 2009 Neuroscience is witnessing increasing knowledge about the anatomy and electrophysiological properties of neurons and their connectivity, leading to an ever increasing computational complexity of neural simulations. At the same time, a rather radical change in personal computer technology emerges with the establishment of multi-cores: high-density ...
Eichner, H., Klug, T., Borst, A.
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BPCM: A Flexible High-Speed Bypass Parallel Communication Mechanism for GPU Cluster
IEEE Access, 2020 With the increasing complexity of computational tasks faced by artificial intelligence technology, the scale of machine learning models continues to expand, and the data volume and frequency of parameter synchronization also increase. This will cause the
Mingjie Wu, Qingkui Chen, Jingjuan Wang
doaj +1 more source
A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures [PDF]
EAI Endorsed Transactions on Industrial Networks and Intelligent Systems, 2018 Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time.
Emmannuel Ofori-Attah +2 more
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A Wideband Fast Start-Up Multi-Core VCO With Auto-Frequency Control in 0.18 μm CMOS
IEEE Access, 2021 A 2.8 – 4.6 GHz wideband multi-core VCO with a fast start-up scheme is presented in this brief. The proposed multi-core VCO uses a successive approximation register based auto frequency control (SAR-AFC) loop with the embedded 2/3 Judge to ensure ...
Yao Li, Bo Zhou, Zuhang Wang
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IEEE Access, 2021 To mitigate the ever worsening “Power wall” and “Memory wall” problems, multi-core architectures with multi-level cache hierarchies have been widely accepted in modern processors.
Ming Ling +3 more
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Multi-core architectures and streaming applications [PDF]
Proceedings of the 2008 international workshop on System level interconnect prediction, 2008 In this paper we focus on algorithms and reconfigurable multi-core architectures for streaming digital signal processing (DSP) applications. The multi-core concept has a number of advantages: (1) depending on the requirements more or fewer cores can be switched on/off, (2) the multi-core structure fits well to future process technologies, more cores ...
Smit, Gerard J.M. +3 more
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