Results 241 to 250 of about 318,553 (304)

A fuzzy graph theoretic approach to face shape recognition using cubic outerplanar structures. [PDF]

Sci Rep
Jaisankar D, Ramalingam S, Zegeye GB.
europepmc   +1 more source

Compute-in-memory implementation of state space models for event sequence processing. [PDF]

Nat Commun
Zhang X, Hu M, Lu S, Kim S, Lee EY, Liu Y, Lu WD.   +6 more
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Evaluating corporate high performance work systems via an intelligent model using complex T spherical fuzzy CoCoSo method. [PDF]

Sci Rep
Liu C.
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Optoelectronic multiple-valued logic implementation

Optics Letters, 1989
A design for optoelectronic multiple-value logic circuits that uses bistable laser diodes or light-emitting diodes is reported. In this multiple-valued logic design, an optoelectronic tristable switching circuit, or light-current mirror, in which two bistable light-emitting diodes are connected in parallel serves as the basic logic element.
S, Liu, C, Li, J, Wu, Y, Liu
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Introduction—Multiple-Valued Logic

IEEE Transactions on Computers, 1986
MULTIPLE-valued logic has been the object of much research over the last fifteen years. Since 1971, there has been an annual symposium devoted exclusively to the subject and, during that time, nearly 600 papers have appeared in its Proceedings. In addition, a large number of technical papers have appeared elsewhere together with a number of survey ...
null Muzio, null Rosenerg
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Implicit Expressibility in Multiple-Valued Logic

Moscow University Computational Mathematics and Cybernetics, 2022
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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Multiple-valued logic design using multiple-valued EXOR

Proceedings 25th International Symposium on Multiple-Valued Logic, 2002
An approach to logic minimization using a new sum operation called multiple valued EXOR is proposed. The paper introduces the multiple valued sum of products expression using the EXOR. As the scheme of the minimization, we utilize an idea based on neural computing.
A. Hozumi, N. Kamiura, Y. Hata, K. Yamato   +3 more
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Flip-Flops for Multiple-Valued Logic

IEEE Transactions on Computers, 1976
A family of multiple-valued (MV) electronic memory elements, referred to herein as flip-flops, is presented along with a system of MV algebra upon which they are based. These MV flip-flops are compared to binary flip-flops. MV asynchronous set-clear flip-flops and synchronous set-clear, D-type, JK, and modulo N counter flip-flops are presented, their ...
Irving, Thurman A. jun., Shiva, Sajjan G., Nagle, H. Troy jun.   +2 more
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Multiple valued logic for microprocessors

Euromicro Newsletter, 1980
Abstract Pin limitation has always been an important problem of Integrated Circuits Packages. In this paper, we examine multiple valued logic as an alternative approach to time multiplexing. TTL and CMOS 4-2 and 2–4 interface circuits are presented and it is shown that 4-valued address, data and coded control lines would solve most of pin limitation ...
D. Etiemble, J.P. Aillaud
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