Results 171 to 180 of about 190,914 (258)
Calorimetric differential pressure sensor with high sensitivity for hydrodynamic perception. [PDF]
Cao Y +8 more
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2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi +3 more
openaire +2 more sources
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi +3 more
openaire +2 more sources
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016
With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
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With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
openaire +2 more sources
A survey of research and practices of Network-on-chip
ACM Computing Surveys, 2006T. Bjerregaard, S. Mahadevan
exaly +2 more sources
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey
Journal of Electronic Testing: Theory and Applications (JETTA), 2023Bahareh Asadi +2 more
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Pitstop: Enabling a Virtual Network Free Network-on-Chip
International Symposium on High-Performance Computer Architecture, 2021Maintaining correctness is of paramount importance in the design of a computer system. Within a multiprocessor interconnection network, correctness is guaranteed by having deadlock-free communication at both the protocol and network levels.
Hossein Farrokhbakht +6 more
semanticscholar +1 more source
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture, 2013Pradip Kumar Sahu +1 more
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An on-chip photonic deep neural network for image classification
Nature, 2021Deep neural networks with applications from computer vision to medical diagnosis1–5 are commonly implemented using clock-based processors6–14, in which computation speed is mainly limited by the clock frequency and the memory access time.
F. Ashtiani +2 more
semanticscholar +1 more source
Securing Network-on-Chip Using Incremental Cryptography
IEEE Computer Society Annual Symposium on VLSI, 2020Network-on-chip (NoC) has become the standard communication fabric for on-chip components in modern System-on-chip (SoC) designs. Since NoC has visibility to all communications in the SoC, it has been one of the primary targets for security attacks ...
Subodha Charles, P. Mishra
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