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Proceedings of the 47th Design Automation Conference, 2010
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential ...
De Micheli G. +5 more
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Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential ...
De Micheli G. +5 more
openaire +4 more sources
2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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Architecting a Secure Wireless Network-on-Chip
ACM/IEEE International Symposium on Networks-on-Chips, 2018With increasing integration in SoCs, the Network-on-Chip (NoC) connecting cores and accelerators is of paramount importance to provide low-latency and high-throughput communication.
Brian Lebiednik +3 more
semanticscholar +1 more source
Computer on a chip and a network of chips
Proceedings of the June 4-8, 1973, national computer conference and exposition on - AFIPS '73, 1973The paper will first discuss the various approaches to a computer on a chip as advanced by the various semiconductor vendors and in the various R&D programs sponsored by the government. This discussion will include a description of the work being performed for the Navy who are developing the technology for a 5000--10,000 gate chip.
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Distributed On-Chip Operating System for Network on Chip
2010 10th IEEE International Conference on Computer and Information Technology, 2010Network on Chip (NoC) is proposed as a promising solution for processors with many cores integrated onto a single chip. The main advantages of NoC are favorable scalability and high bandwidth for on-chip cores and communications. However, OS designed for NoC have not been fully researched to date. Because the microkernel operating system is composed of
Wei Hu 0001 +4 more
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A New On-Chip Interconnection Network for System-on-Chip
2008 International Conference on Embedded Software and Systems, 2008With the feature size of semiconductor technology reducing and intellectual properties (IP) cores increasing, on chip communication architectures have a great influence on the performance and area of system-on-chip (SoC) design. Network-on-chip (NoC) has been proposed as a promising solution to complex SoC communication problems and has been widely ...
Youyao Liu, Jungang Han, Huimin Du
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Network-on-Chip for Turbo Decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High ...
Yang, Qingqing +3 more
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Optical Interconnects for Network on Chip
2006 1st International Conference on Nano-Networks and Workshops, 2006This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS microchips.
Scandurra A. +4 more
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Secure model checkers for Network-on-Chip (NoC) architectures
ACM Great Lakes Symposium on VLSI, 2016As chip multiprocessors (CMPs) are becoming more susceptible to process variation, crosstalk, and hard and soft errors, emerging threats from rogue employees in a compromised foundry are creating new vulnerabilities that could undermine the integrity of ...
T. Boraten +2 more
semanticscholar +1 more source
2009
The increasing integration densities made available by shrinking of device geometries will have to be exploited to meet the computational requirements of applications from different domains, such as multimedia processing, high-end gaming, biomedical signal processing, advanced networking services, automotive, or ambient intelligence. Interestingly, the
Gilabert F. +3 more
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The increasing integration densities made available by shrinking of device geometries will have to be exploited to meet the computational requirements of applications from different domains, such as multimedia processing, high-end gaming, biomedical signal processing, advanced networking services, automotive, or ambient intelligence. Interestingly, the
Gilabert F. +3 more
openaire +3 more sources