Results 211 to 220 of about 124,522 (260)
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1993 Euromicro Workshop on Parallel and Distributed Processing, 2002
Reports on the successful fabrication of a network chip for large-scale parallel computers. It provides extremely low-latency message delivery in grids of up to 1024 processors or toruses of up to 256 processors. Larger arrays can be constructed using an address embedding technique and the gateway channels supported by the chip.
Chris R. Jesshope, Cruz Izu
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Reports on the successful fabrication of a network chip for large-scale parallel computers. It provides extremely low-latency message delivery in grids of up to 1024 processors or toruses of up to 256 processors. Larger arrays can be constructed using an address embedding technique and the gateway channels supported by the chip.
Chris R. Jesshope, Cruz Izu
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IEEE Design & Test of Computers, 2005
As SoCs continue down the path to smaller geometries and higher integration, their performance measures are changing dramatically. The larger the chip, the greater the disparity between local logic speeds and their interconnect latencies. This issue explores on-silicon integration, discussing challenges in networks on chips, various NoC architectures ...
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As SoCs continue down the path to smaller geometries and higher integration, their performance measures are changing dramatically. The larger the chip, the greater the disparity between local logic speeds and their interconnect latencies. This issue explores on-silicon integration, discussing challenges in networks on chips, various NoC architectures ...
openaire +1 more source
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016
With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
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With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
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2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016
General purpose chip multiprocessors (CMP) are challenging to on-chip intercommunication network designers since one would need low latency, high bandwidth independently of the communication patterns, support for cost-efficient synchronization, and low energy consumption to support arbitrary applications.
Forsell, Martti +3 more
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General purpose chip multiprocessors (CMP) are challenging to on-chip intercommunication network designers since one would need low latency, high bandwidth independently of the communication patterns, support for cost-efficient synchronization, and low energy consumption to support arbitrary applications.
Forsell, Martti +3 more
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IEEE Design and Test of Computers, 2005
A few years ago, Sun Microsystems used the slogan, "the network is the computer," to promote its products and to alert people to a profound change in computing-use models. With the growth in cell phones, digital cameras, portable music players, wireless e-mail, GPS sensors, and automotive map displays that rely on wired and wireless networks, you might
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A few years ago, Sun Microsystems used the slogan, "the network is the computer," to promote its products and to alert people to a profound change in computing-use models. With the growth in cell phones, digital cameras, portable music players, wireless e-mail, GPS sensors, and automotive map displays that rely on wired and wireless networks, you might
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Computer on a chip and a network of chips
Proceedings of the June 4-8, 1973, national computer conference and exposition on - AFIPS '73, 1973The paper will first discuss the various approaches to a computer on a chip as advanced by the various semiconductor vendors and in the various R&D programs sponsored by the government. This discussion will include a description of the work being performed for the Navy who are developing the technology for a 5000--10,000 gate chip.
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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Network-on-Chip for Turbo Decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High ...
Yang, Qingqing +3 more
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Optical Interconnects for Network on Chip
2006 1st International Conference on Nano-Networks and Workshops, 2006This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS microchips.
Scandurra A. +4 more
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2009
The increasing integration densities made available by shrinking of device geometries will have to be exploited to meet the computational requirements of applications from different domains, such as multimedia processing, high-end gaming, biomedical signal processing, advanced networking services, automotive, or ambient intelligence. Interestingly, the
Gilabert F. +3 more
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The increasing integration densities made available by shrinking of device geometries will have to be exploited to meet the computational requirements of applications from different domains, such as multimedia processing, high-end gaming, biomedical signal processing, advanced networking services, automotive, or ambient intelligence. Interestingly, the
Gilabert F. +3 more
openaire +3 more sources