Results 201 to 210 of about 190,914 (258)
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Layered Switching for Networks on Chip
2007 44th ACM/IEEE Design Automation Conference, 2007We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture.
Zhonghai Lu, Ming Liu 0011, Axel Jantsch
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Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
International Conference on Architectural Support for Programming Languages and Operating Systems, 2018Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency ...
Maciej Besta +5 more
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Network-on-Chip Design for Gigascale Systems-on-Chip
2004The Industrial Information Technology Handbook focuses on existing and emerging industrial applications of IT, and on evolving trends that are driven by the needs of companies and by industry-led consortia and organizations. Emphasizing fast growing areas that have major impacts on industrial automation and enterprise integration, the Handbook covers ...
BERTOZZI, DAVIDE +2 more
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On-Chip Interconnection Networks of the TRIPS Chip
IEEE Micro, 2007Paul Gratz +6 more
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IETE Technical Review, 2013
AbstractMore and more applications are hungry for more and more computation power and performance. This need plus the technology advancements in the field of electronics are resulting in more and more cores and processors being put on the smaller and smaller System-on-Chip (SoC).
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AbstractMore and more applications are hungry for more and more computation power and performance. This need plus the technology advancements in the field of electronics are resulting in more and more cores and processors being put on the smaller and smaller System-on-Chip (SoC).
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10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007
Erno Salminen +2 more
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Erno Salminen +2 more
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A network on chip architecture and design methodology
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002, 2002Shashi Kumar +7 more
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Scalable Design and Synthesis of 3D Mesh Network on Chip
, 2017Arpit Jain +3 more
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Cycle-Accurate Network on Chip Simulation with Noxim
ACM Transactions on Modeling and Computer Simulation, 2016V. Catania +4 more
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Path-Diversity-Aware Fault-Tolerant Routing Algorithm for Network-on-Chip Systems
IEEE Transactions on Parallel and Distributed Systems, 2017Yu-Yin Chen +4 more
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