Results 201 to 210 of about 124,522 (260)

3D Vessels-on-Chip using isogenic hiPSC-derived VSMCs reveal NOTCH3-driven alterations in brain small vessel disease. [PDF]

Stem Cell Reports
Vila Cuenca M, Tsikari T, Cerfontaine MN, Gallant JL, van den Hil FE, Bouma MJ, Dijkstra KL, Gravesteijn G, de Vries AAF, Mummery CL, Rutten JW, Lesnik Oberstein SAJ, Orlova VV.   +12 more
europepmc   +1 more source

Microcomb-enabled parallel self- calibration optical convolution streaming processor. [PDF]

Light Sci Appl
Wang J, Xu X, Zhu X, Xu Y, Chen S, Zhang H, Zheng Y, Li S, Bai Y, Liu Z, Morandotti R, Little BE, Chu ST, Lowery AJ, Moss DJ, Xu K.   +15 more
europepmc   +1 more source

A thermal resistance prediction model for heterogeneous integrated chips incorporating an AI-based BP neural network. [PDF]

Sci Rep
Li Y, Xu S, Guo L.
europepmc   +1 more source

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Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey

Journal of Electronic Testing: Theory and Applications (JETTA), 2023
Syed Maqsood Zia, Bahareh Asadi, Asghar Mohamadian   +2 more
exaly   +2 more sources

The Chip Is the Network: Toward a Science of Network-on-Chip Design

Foundations and Trends® in Electronic Design Automation, 2009
The Chip Is the Network: Towards a Science of Network-on-Chip Design reviews the major design methodologies that have had a profound effect on designing future Network-on-Chip (NoC) architectures. More precisely, it addresses the problem of NoC design in the deterministic context, where the application and the architecture are modeled as graphs with ...
Radu Marculescu, Paul Bogdan
openaire   +1 more source

Network-on-Chip virtualization in Chip-Multiprocessor Systems

Journal of Systems Architecture, 2012
[EN] It is expected that Chip Multiprocessor Systems (CMPs) will contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. In order to obtain a good CMP utilization several applications will need to coexist in the system and in those cases virtualization of the CMP system will become ...
Francisco Triviño, José L. Sánchez 0002, Francisco J. Alfaro, José Flich   +3 more
openaire   +4 more sources

Routerless Network-on-Chip

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen   +3 more
openaire   +1 more source

Sensor Network-On-Chip

2007 International Symposium on System-on-Chip, 2007
In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed
Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones   +3 more
openaire   +1 more source

Universal On-Chip Network Simulator for Networks-on-Chip Development

2021 International Russian Automation Conference (RusAutoCon), 2021
This work is devoted to Universal On-Chip Network Simulator (UOCNS) for Network-on-Chip (NoC) development. The principle of the topological approach in NoC design was analyzed. A review of high-level NoC simulators was done. A complete analysis of the structure of UOCNS and its main components was carried out, as well as it was tested on different ...
A. A. Amerikanov, A. S. Ponomarev
openaire   +1 more source