Results 11 to 20 of about 22,805 (227)
IET Power Electronics, EarlyView., 2022 This paper introduces the research on the inductance‐capacitor‐capacitor‐inductance grid‐connected inverter using active disturbance rejection and grid voltage feedforward coordinated control technology. The pade approximation is performed on the inductance‐capacitor‐capacitor‐inductance filter to derive the first‐order discretization mathematical ...
Guang‐Xin Zhong +4 more
wiley +1 more source
IET Power Electronics, EarlyView., 2023 An innovative switched‐capacitor‐based inverter is proposed in this article. The suggested converter can produce a five‐level output voltage by utilizing minimal components (single dc source, six switches, and one capacitor). The effectiveness of the suggested inverter is verified by experimental results using hardware in loop OPAL‐RT OP4510.
Tamiru Debela +2 more
wiley +1 more source
A high performance grid synchronization method for renewable energy grid-connected applications
Energy Reports, 2021 Aiming at the problem of insufficient harmonic suppression capability for distributed renewable energy grid-connected application equipments, an efficient grid synchronous phase-locked loop(PLL) which will suppress harmonics is proposed. Firstly, a novel
Nanmu Hui, Haixiang Xu, Yingying Feng
doaj +1 more source
Estimator Parameter Tegangan Jaringan Tiga Fasa Berbasis D-SOGI PLL
Majalah Ilmiah Teknologi Elektro, 2017 Phase locked loop (PLL) adalah sebuah sistem umpan balik yang memegang peran penting dalam sistem-sistem konverter terkoneksi jaringan listrik. Fungsi utama PLL adalah mendapatkan beragam informasi parameter jaringan yaitu seperti phase dan magnitude ...
Iwan Setiawan +3 more
doaj +1 more source
Electronics Letters, 2022 The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability.
Ryoga Iwashita +3 more
doaj +1 more source
Adaptive Impedance-Conditioned Phase-Locked Loop for the VSC Converter Connected to Weak Grid
Energies, 2021 In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by ...
Mostafa A. Hamood +2 more
doaj +1 more source
A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2 [PDF]
, 2009 This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2
Bohsali, Mounhir +3 more
core +3 more sources
Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops [PDF]
, 2009 This brief analyzes the jitter as well as the power dissipation of phase-locked loops (PLLs). It aims at defining a benchmark figure-of-merit (FOM) that is compatible with the well-known FOM for oscillators but now extended to an entire PLL.
Gao, X. +3 more
core +2 more sources
Journal of Modern Power Systems and Clean Energy, 2023 Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an
Yongqing Meng +5 more
doaj +1 more source
A fuzzy-based hybrid PLL scheme for abnormal grid conditions [PDF]
, 2015 This paper presents a new family of fuzzy phase locked loop (FPLL) -fuzzy double decouple synchronous reference frame phase locked loop (FDDSRF-PLL)- that incorporated DDSRF-PLL into FPLL. FDDSRF-PLL enjoys both advantageous of DDSRF-PLL and fuzzy system
Beheshtaein, Siavash +2 more
core +2 more sources