Results 21 to 30 of about 2,127 (187)
IEEE Access, 2023 The study of stability criterion and interaction analysis for grid-connected inverter under weak grid is of great value. The previous stability criterion combined current loop, phase-locked loop and other loops together, and used the same external ...
Fang Liu +4 more
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Radar Waveform Generator with Fuzzy Frequency Regulation [PDF]
International Journal of Telecommunications: The Phase-Locked Loop (PLL) is a common functional component in many electrical systems. Phase-locked loops (PLLs) are closed-loop feedback-driven devices producing a signal depending on the frequency and phase of reference sig-nal that comes in.
Ahmed Salem +2 more
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Design of wind power grid-connected monitoring system based on DSP data collection
Nantong Daxue xuebao. Ziran kexue ban, 2022 Distributed new energy power generation is highly valued for avoiding energy consumption caused by long distance transmission. As a grid-accessed supporting product, grid-connected controllers enjoy a large market demand.Based on the grid-accessed ...
ZHU Jianhong, GU Juping, REN Haofeng, CHEN Zeyu
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FPGA implementation of impedance-compensated phase-locked loop for HVDC converters
The Journal of Engineering, 2018 The phase-locked loop (PLL) plays a key role in HVDC systems. Recently, a new type of PLL called the impedance-compensated phase-locked loop (IC-PLL) was introduced to compensate for the voltage drop across the AC network's Thevenin impedance, making the
Yue Yi +2 more
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IEEE Access, 2020 This paper reports a millimeter (mm)-wave type-II dual-loop phase-locked loop (PLL) with low-power and low-complexity design for improving jitter-power performance and power efficiency.
Zunsong Yang +4 more
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A Generative Neuro‐Symbolic AI for Protein Sequence Design
Advanced Science, EarlyView.We introduce EffieDes, a neuro‐symbolic framework coupling deep learning‐based fitness landscape parameterization with exact automated reasoning. Unlike greedy sampling, EffieDes identifies sequences that globally optimize fitness while satisfying intricate design constraints.
Marianne Defresne +12 more
wiley +1 more source
International Journal of Circuit Theory and Applications, EarlyView.A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia +3 more
wiley +1 more source
Design of a fast-acquisition phase-locked loop for frequency control systems
Dianzi Jishu YingyongPhase-locked loop (PLL) is a negative feedback control system that can achieve phase synchronization of two signals. Its filtering effect can make its passband narrow, and its output frequency automatically track the input frequency.
Chang Jian +4 more
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International Journal of Circuit Theory and Applications, EarlyView.A ramp‐based phase‐locked loop (RPLL) active rectifier operating at 40.68 MHz compensates switching delay variations to improve phase alignment. The proposed architecture achieves 90.3% peak power conversion efficiency and 98.0% voltage conversion ratio for high‐frequency wireless power transfer in implantable medical devices.
Woorim Lee +5 more
wiley +1 more source
Energy Science &Engineering, EarlyView.This graphical abstract illustrates the evolution of wireless electric vehicle charging from unidirectional wireless power transfer to bidirectional wireless power transfer (BWPT) and toward future intelligent, autonomous wireless energy systems.
P. V. Elumalai +6 more
wiley +1 more source