Phase Locked Loop Test Methodology [PDF]
, 2008 Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based.
Burbidge, Martin, Richardson, Andrew
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Techniques for automatic on chip closed loop transfer function monitoring for embedded charge pump phase locked loops. [PDF]
, 2003 Charge Pump Phase locked loops are used in a variety of applications, including on chip clock synthesis, symbol timing recovery for serial data streams, and generation of frequency agile high frequency carrier signals.
Burbidge, Martin J. +2 more
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Noise performance of frequency- and phase-locked CW magnetrons operated as current-controlled oscillators. [PDF]
, 2005 Low-power continuous wave ``cooker'' magnetrons driven from industrial-quality switch-mode power supplies have been frequency locked by driving them as current-controlled oscillators in a phase-lock loop (PLL).
Carter, Richard G. +2 more
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Enhanced Single-phase Phase Locked Loop based on Complex-Coefficient Filter [PDF]
, 2022 Complex coefficient filters (CCFs) are widely used for phase-locked loop (PLL) in three-phase power systems, while its usage is largely sparse in the single-phase domain.
Gautam, Samir +12 more
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A high performance grid synchronization method for renewable energy grid-connected applications
Energy Reports, 2021 Aiming at the problem of insufficient harmonic suppression capability for distributed renewable energy grid-connected application equipments, an efficient grid synchronous phase-locked loop(PLL) which will suppress harmonics is proposed. Firstly, a novel
Nanmu Hui, Haixiang Xu, Yingying Feng
doaj +1 more source
DC offset elimination method of Phase-locked loop based on novel generalized integrator
Energy Reports, 2021 When the renewable energy power is connected to the grid, distortion voltage interference and grid voltage frequency fluctuation will occur, which will cause the inverter output current to be abnormal.
Nanmu Hui, Yingying Feng, Xiaowei Han
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Electronics Letters, 2022 The quantisation noise contribution of a conventional FDC phase‐locked loop (PLL) is still high due to the only second‐order noise‐shaping capability.
Ryoga Iwashita +3 more
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Adaptive Impedance-Conditioned Phase-Locked Loop for the VSC Converter Connected to Weak Grid
Energies, 2021 In this paper, an adaptive version of the impedance-conditioned phase-locked loop (IC-PLL), namely the adaptive IC-PLL (AIC-PLL), is proposed. The IC-PLL has recently been proposed to address the issue of synchronisation with a weak AC grid by ...
Mostafa A. Hamood +2 more
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Journal of Modern Power Systems and Clean Energy, 2023 Voltage source converter based high-voltage direct current (VSC-HVDC) transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources. However, connecting a voltage source converter (VSC) to an
Yongqing Meng +5 more
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Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter [PDF]
, 2011 Bang-bang phase-locked loops (BBPLLs) are inherently nonlinear systems due to the binary phase detector (BPD). While they are typically used for clock and data recovery, the ongoing trend toward digital loop implementations has resulted in several ...
Tertinek, Stefan +3 more
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