Results 211 to 220 of about 78,217 (266)

A new poly-Si TFT to improve surface roughness at poly-oxide/poly-Si interface

Physica Scripta, 1997
We have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. The surface roughness at the interface is observed by transmission electron microscopy (TEM) and is also evaluated by atomic force microscopy (AFM) after the oxide layer is removed ...
Byung-Hyuk Min, Cheol-Min Park, Juhn-Suk Yoo, Min-Koo Han   +3 more
openaire   +1 more source

A new poly-Si thin-film transistor with poly-Si/a-Si double active layer

IEEE Electron Device Letters, 2000
A new poly-Si TFT employing a rather thick poly-Si (400 /spl Aring/)/a-Si(4000 /spl Aring/) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the
null Kee-Chan Park, null Kwon-Young Choi, null Juhn-Suk Yoo, null Min-Koo Han   +3 more
openaire   +1 more source

Electrical characteristics of poly-Si TFT's with smooth surface roughness at oxide/poly-Si interface

IEEE Transactions on Electron Devices, 1997
We have fabricated a polycrystalline silicon thin film transistor (poly Si TFT) using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFT's fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable ...
null Byung-Hyuk Min, null Cheol-Min Park, null Min-Koo Han   +2 more
openaire   +1 more source

Electrical properties of TiSi2 clusters in poly Si

Microelectronic Engineering, 2002
Clusters of TiSi were formed in a polysilicon matrix by thermal annealing of a Ti-Si multilayer structure. The silicide grain size was varied by suitable thermal treatments. The DC electrical resistivity of the composite material has been measured in the 4-500 K temperature range by van der Pauw technique.
PIRO A. M, ALESSANDRINO M. S, BONGIORNO C, LA VIA F, SPINELLA C, GRIMALDI, Maria Grazia   +5 more
openaire   +4 more sources

Silicon Epitaxial Growth on Poly-Si Film by HWCVD for Low-Temperature Poly-Si TFTs

Journal of The Electrochemical Society, 2007
A two-step process consisting of the preparation of poly-Si seed film by vapor-induced crystallization and the growth of an epitaxial Si layer on the poly-Si seed film via hot-wire chemical vapor deposition (HWCVD) is introduced to obtain a high-quality poly-Si film at a temperature below 500°C.
Lee, SR Lee, Seung Ryul, Ahn, KM Ahn, Kyung Min, Ahn, BT Ahn, Byung Tae   +2 more
openaire   +2 more sources

30.4: Short‐Channel Effect of Sub‐Micron Poly‐Si TFTs with Large Poly‐Si Grains

SID Symposium Digest of Technical Papers, 1998
Abstract To study 3 V‐driven LSI‐like TFTs, we fabricated high‐temperature n‐channel poly‐Si TFTs, some of which had a subthreshold slope of 90 mV/dec and an electron field mobility of 432 cm 2 /Vs, with submicron channel length and large poly‐Si grains.
H. Akimoto, M. Hatano, T. Sakai
openaire   +1 more source

Poly-Si peripheral circuits and contact properties of laser processed poly-Si thin film transistors

Proceedings of 4th International Conference on Solid-State and IC Technology, 2002
Monolithic fabrication of a-Si:H and poly-Si TFTs with a dual dielectric gate insulator and the effect of source-drain contact resistance on poly-Si transistor performance are discussed. A dual dielectric gate insulator provides the correct threshold voltages for both a-Si and poly-Si TFTs, thereby simplifying the fabrication processes.
P. Mei, J.B. Boyce, D.K. Fork, M. Hack, R. Lujan, S.E. Ready   +5 more
openaire   +1 more source

Effects of Poly-Si Annealing on Gate Oxide Charging Damage in Poly-Si Gate Etching Process

MRS Proceedings, 2002
AbstractThe effects of the poly-Si annealing on gate oxide charging damage in the gate etching process were investigated. Our electrical test results show that gate oxide charging damage can be reduced if the poly-Si is not annealed prior to the gate etching process.
Daniel Chong, Won Jong Yoo, Lap Chan, Alex See   +3 more
openaire   +1 more source

53.3: Multisync Poly‐Si AMLCD

SID Symposium Digest of Technical Papers, 2000
Abstract We propose a new scan driver circuit to implement multi display mode(mutisync function), which uses an identical conventional scan driver circuit without an additional circuit. The new scheme is simple and takes a small area, compared with the prior schemes for multisync mode.
I. G. Kim, H. H. Lee, D. H. Kim, W. Y. Park, B. H. Min, J. H. Souk, B. H. Jung   +6 more
openaire   +1 more source

Laser crystallised poly-Si TFTs

Microelectronic Engineering, 1992
Layers of ?Si:H have been crystallised into poly-Si using a pulsed KrF excimer laser. Examination of the these layers by cross-sectional TEM has revealed a vertically stratified microstructure, with a large grain surface region crystallising from the molten phase.
SD Brotherton, DJ McCulloch, JP Gowers, A Gill   +3 more
openaire   +1 more source