Results 211 to 220 of about 60,987 (263)

CRISC Configurable Reduced Instruction Set Computer or Complex Reconfigurable Instruction Set Computer

Microprocessing and Microprogramming, 1988
Abstract For the design of a multiple purpose high performance multiprocessor, it is necessary to combine firmware and software research into a single project. This paper describes the options taken in the multicomputer project at the department INFO of the University of Brussels (VUB).
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Reduced Instruction Set Computers

1996
Two of the best known families of microprocessor are those based on the Motorola 68000 and Intel 8086 architectures, the 680×0 family gaining popularity through its association with the Apple Macintosh and the 80×86 family through association with the original IBM PC.
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In2Core: Leveraging Influence Functions for Coreset Selection in Instruction Finetuning of Large Language Models

Conference on Empirical Methods in Natural Language Processing
Despite advancements, fine-tuning Large Language Models (LLMs) remains costly due to the extensive parameter count and substantial data requirements for model generalization.
Ayrton San Joaquin, Bin Wang, Zhengyuan Liu, Nicholas Asher, Brian Lim, Philippe Muller, Nancy F. Chen   +6 more
semanticscholar   +1 more source

Reduced-Instruction-Set, Writable-Instruction-Set and Very-Long-Instruction-Word Computers [PDF]

, 1991
Instruction sets and their addressing modes and functional classes may grow to be quite complicated. For example, the widely used minicomputer VAX 11/780 has 16 addressing modes and more than 300 unique instructions! Even microprocessors often have complicated instruction sets. The Motorola 68020 recognizes seven data types, employs 18 addressing modes,
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A residue number system reduced instruction set computer (RISC) concept

International Conference on Acoustics, Speech, and Signal Processing, 2003
A reduced-instruction-set RNS (residue number system) processor is proposed for digital signal processing algorithms. Issues leading toward a RNS RISC are examined, namely suitable RNS algorithms. It is argued that this is a reasonable next step in RNS research.
Fred J. Taylor, M. Griffin
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Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

Sādhanā, 2023
Manan Jain, Het Kanzariya, Neel Joshi, Yesha Masharu, Sachin Gajjar, Dhaval Shah   +5 more
semanticscholar   +1 more source

Multiple register sets for VLSI reduced instruction set computers : a performance analysis

2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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Real time, nonintrusive instrumentation of reduced instruction set computer (RISC) microprocessors

Proceedings of the IEEE 1992 National Aerospace and Electronics Conference@m_NAECON 1992, 2003
It is noted that real-time, nonintrusive instrumentation (RTNI) of high-performance RISC (reduced-instruction-set computer) microprocessors will be very difficult without some on-chip circuitry to support the event detection and data acquisition logic used to distinguish instruction execution flow and data generation and usage.
D.D. Beeson, M.T. Michael, W.J. Cannon
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Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

Concurrency and Computation: Practice and Experience, 2012
SUMMARYThe popularity of multimedia applications made them a major theme in embedded systems. The key component for supporting multimedia application well is embedded processor. Thus, we have designed and implemented an embedded processor, called UniDual processor, to achieve this objective.
Cheng-Yu Lee, Rong-Guey Chang, Min-Chin Hung   +2 more
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Ada on reduced instruction set computers, for real-time embedded systems

9th IEEE/AIAA/NASA Conference on Digital Avionics Systems, 2002
The 32-bit reduced-instruction-set-computer (RISC)-based processors have been identified by the Joint Integrated Avionics Working Group as a potential successor to the MIL-STD-1750A 16-bit processor for military applications. It is pointed out that there are a number of important performance issues associated with using high-order languages such as Ada
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