Results 221 to 230 of about 178,264 (269)

Reduced Instruction Set Computers Then and Now

Computer, 2017
A widely cited Computer article published in 1982 described the reduced instruction set computer (RISC) as an alternative to the general trend at the time toward increasingly complex instruction sets. A RISC executes most instructions in a single short cycle.
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Real time, nonintrusive instrumentation of reduced instruction set computer (RISC) microprocessors

Proceedings of the IEEE 1992 National Aerospace and Electronics Conference@m_NAECON 1992, 2003
It is noted that real-time, nonintrusive instrumentation (RTNI) of high-performance RISC (reduced-instruction-set computer) microprocessors will be very difficult without some on-chip circuitry to support the event detection and data acquisition logic used to distinguish instruction execution flow and data generation and usage.
W.J. Cannon, M.T. Michael, D.D. Beeson
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Architecture tradeoffs in in reduced instruction set computers: a case study

IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing. Proceedings, 2002
A major problem facing computer architects is the development of methods and techniques that measure and predict the performance of their architectures. This problem arises also in designing reduced instruction set computers (RISCs). The paper studies the effect of machine instruction set on performance of a subset of RISC architectures. In particular,
H. ElGebaly, M. Abd-El-Barr, C. McCrosky
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VLSI Implementations of a Reduced Instruction Set Computer

1981
A general trend in computers today is to increase the complexity of architectures commensurate with the increasing potential of implementation technologies. Consequences of this complexity are increased design time, more design errors, inconsistent implementations, and the delay of single chip implementation[7].
Daniel T. Fitzpatrick, Manolis G. H. Katevenis, David A. Patterson, Zvi Peshkess, Robert W. Sherburne, John K. Foderaro, Howard A. Landman, James B. Peek, Carlo H. Séquin, Korbin S. Van Dyke   +9 more
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Multiple register sets for VLSI reduced instruction set computers : a performance analysis

2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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A perspective on the 801/Reduced Instruction Set Computer

IBM Systems Journal, 1987
From the earliest days of computers until the early 1970s, the trend in computer architecture was toward increasing complexity. This complexity revealed itself through the introduction of new instructions that matched the application areas. Microcode was an implementation technique that greatly facilitated this trend; thus, most computers were ...
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F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed.
C.K. Tien, C.C. Poon, H. Greub, J.F. McDonald   +3 more
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Reduced-Instruction-Set, Writable-Instruction-Set and Very-Long-Instruction-Word Computers

1991
Instruction sets and their addressing modes and functional classes may grow to be quite complicated. For example, the widely used minicomputer VAX 11/780 has 16 addressing modes and more than 300 unique instructions! Even microprocessors often have complicated instruction sets. The Motorola 68020 recognizes seven data types, employs 18 addressing modes,
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Ada on reduced instruction set computers, for real-time embedded systems

9th IEEE/AIAA/NASA Conference on Digital Avionics Systems, 2002
The 32-bit reduced-instruction-set-computer (RISC)-based processors have been identified by the Joint Integrated Avionics Working Group as a potential successor to the MIL-STD-1750A 16-bit processor for military applications. It is pointed out that there are a number of important performance issues associated with using high-order languages such as Ada
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Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

Concurrency and Computation: Practice and Experience, 2012
SUMMARYThe popularity of multimedia applications made them a major theme in embedded systems. The key component for supporting multimedia application well is embedded processor. Thus, we have designed and implemented an embedded processor, called UniDual processor, to achieve this objective.
Cheng‐Yu Lee, Min‐Chin Hung, Rong‐Guey Chang   +2 more
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