Results 131 to 140 of about 716 (180)

Tiered-ReRAM: A Low Latency and Energy Efficient TLC Crossbar ReRAM Architecture

2019 35th Symposium on Mass Storage Systems and Technologies (MSST), 2019
Resistive Memory (ReRAM) is promising to be used as high density storage-class memory by employing Triple-Level Cell (TLC) and crossbar structures. However, TLC crossbar ReRAM suffers from high write latency and energy due to the IR drop issue and the iterative program-and-verify procedure.
Yang Zhang 0051, Dan Feng 0001, Wei Tong 0001, Jingning Liu, Chengning Wang, Jie Xu 0013   +5 more
openaire   +1 more source

Learning the sparsity for ReRAM

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
With the in-memory processing ability, ReRAM based computing gets more and more attractive for accelerating neural networks (NNs). However, most ReRAM based accelerators cannot support efficient mapping for sparse NN, and we need to map the whole dense matrix onto ReRAM crossbar array to achieve O(1) computation complexity.
Jilan Lin, Zhenhua Zhu 0002, Yu Wang 0002, Yuan Xie 0001   +3 more
openaire   +2 more sources

Tileable Monolithic ReRAM Memory Design

2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2020
Non-volatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU’s die. ReRAM bitcells are fabricated within crosspoint sub-arrays that leave the bulk of transistors underneath the sub-arrays vacant.
Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung   +7 more
openaire   +1 more source

ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator

2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021
Deep Neural Networks (DNNs) have gained a strong momentum across various applications in recent years. Meanwhile, they are compute- and memory-intensive as the deep layers induce massive matrix-multiplication operations. The Resistive Random Access Memory (ReRAM) can naturally carry out the matrix-multiplication in memory.
Zhuoran Song, Dongyue Li, Zhezhi He, Xiaoyao Liang, Li Jiang 0002   +4 more
openaire   +1 more source

On the origin of the fading memory effect in ReRAMs

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017
Redox-based resistive switching devices can be switched between a high resistance state and a low resistance state in a reversible manner. An important requirement is the stable operation between these two states for a high amount of switching cycles.
S. Menzel, R. Waser, A. Siemon, C. La Torre, M. Schulten, R. Waser, A. Ascoli, R. Tetzlaff   +7 more
openaire   +2 more sources

ReRAM for Embedded Application: A Review

2021 International Symposium on Electronics and Smart Devices (ISESD), 2021
Recent developments in memory devices have given rise to many ideas about the need for more specific memory characteristics in new devices. This paper discusses the results of reviews of several papers regarding the comparison of ReRAM benchmarks in their application which aims to determine the characteristics of embedded ReRAM (eReRAM) further against
Muhammad Arbi Minanda, Muhammad Fakhrudin, Mochammad Rizky Abadi Sutoyo, Muhamad Amin Sulthoni   +3 more
openaire   +1 more source

Leveraging Capacitance Modulation of ReRAM for CMOS-ReRAM Image Sensor

2025 Device Research Conference (DRC)
The rapid expansion of applications in the Internet of Things, biomedical imaging, unmanned aerial vehicle imaging, and smart devices drives the increasing demand for advanced image sensors. Conventional CMOS image sensors (CIS) are widely employed in these domains but are limited by their relatively low dynamic range (DR).
Chourasia, S., Pande, S., Padovani, A., Chakrabarti, B.   +3 more
openaire   +1 more source

Approximate in-Memory Computing on ReRAM Crossbars

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS), 2019
Existing capabilities of computing devices are unable to match the growing demands of modern computing tasks such as multimedia processing, artificial intelligence, pattern matching, and data mining etc. Towards this end, advancements have been made in approximate hardware and software designs for such error tolerant, soft applications.
Amad Ul Hassen, Salman Anwar Khokhar
openaire   +2 more sources

The background of ReRAM devices

2021
In this chapter, we will first introduce the characteristics of resistive random-access memory (ReRAM) devices. Post-characterization of the ReRAMs, we introduce the structural design of the ReRAMs followed by a few applicational designs of ReRAMbased devices.
openaire   +1 more source

ReRAM-based accelerator for deep learning

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018
Big data computing applications such as deep learning and graph analytic usually incur a large amount of data movements. Deploying such applications on conventional von Neumann architecture that separates the processing units and memory components likely leads to performance bottleneck due to the limited memory bandwidth.
Bing Li 0017, Linghao Song, Fan Chen 0001, Xuehai Qian, Yiran Chen 0001, Hai Helen Li   +5 more
openaire   +2 more sources