Results 201 to 210 of about 13,809 (235)
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Podpora RISC-V v MSIMu

2023
In this thesis we have added support for RISC-V into the MSIM emulator. MSIM supported only the MIPS R4000 as a CPU, and has been used for teaching the Operating systems course. This project redesigns MSIM to support multiple CPU architectures and adds an implementation of a RISC-V CPU. RISC-V as an architecture provides a basic instruction set as well
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Automotive RISC-V Collaboration

New Electronics, 2021
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Confidential Computing on RISC-V

Getting confidential computing right is a tough challenge. Other architectures already tried in the past to introduce mechanisms for providing confidentiality guarantees, and in many cases failed. On RISC-V the Confidential Computing SIG, under the Security HC, is working on two specifications for providing confidentiality guarantees for VMs/TEEs and ...
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A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications

IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
Yifan Zhao, Ruiqi Xie, Guozhu Xin
exaly  

Emoji shellcoding in RISC-V

2023 IEEE Security and Privacy Workshops (SPW), 2023
Hadrien Barral   +2 more
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RISC-V SOC Verification

New Electronics, 2021
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CORDIC Accelerator for RISC-V

2021 29th Telecommunications Forum (TELFOR), 2021
Recep Onur Yildiz, Ayse Yilmazer-Metin
openaire   +1 more source

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

Transactions on Architecture and Code Optimization, 2023
, Oscar Palomar, Osman S Unsal
exaly  

Model procesoru RISC-V

The number of application specific instruction set processors is rapidly increasing, because of increased demand for low power and small area designs. A lot of new instruction sets are born, but they are usually confidential. University of California in Berkeley took an opposite approach. The RISC-V instruction set is completely free.
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A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications

IEEE Transactions on Emerging Topics in Computing, 2022
Marco Cococcioni   +2 more
exaly  

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