A Unified PUF and Crypto Core Exploiting the Metastability in Latches
Future Internet, 2022 Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations.
Ronaldo Serrano +5 more
doaj +1 more source
Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
Cryptography, 2022 The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
doaj +1 more source
CoVE: Towards Confidential Computing on RISC-V Platforms [PDF]
ACM International Conference on Computing Frontiers, 2023 Multi-tenant computing platforms are typically comprised of several software and hardware components including platform firmware, operating system, virtualization monitor, and tenant workloads (typically in a virtual machine, container, or application ...
R. Sahita +7 more
semanticscholar +1 more source
Evaluation of Coverage Metrics for Assessing Test Suite Effectiveness in RISC-V Core Verification [PDF]
, 2023 RISC-V is a popular open-source Instruction Set Architecture (ISA) that is gaining widespread adoption in the industry. The verification of a RISC-V core involves a rigorous testing process to ensure that it meets the functional requirements of the ISA ...
Chippagi, Harinagarjun
core +2 more sources
A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge [PDF]
Asia and South Pacific Design Automation Conference, 2023 Extreme edge platforms, such as in-vehicle smart devices, require efficient deployment of quantized deep neural networks (DNNs) to enable intelligent applications with limited amounts of energy, memory, and computing resources. However, many edge devices
Longwei Huang +4 more
semanticscholar +1 more source
A RISC-V Processor Design for Transparent Tracing [PDF]
Electronics, 2020 Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code
Gamino del Río, Iván +7 more
openaire +2 more sources
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET [PDF]
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)We present Occamy, a 432-core RISC-V dual-chiplet 2.5D system for efficient sparse linear algebra and stencil computations on FP64 and narrow (32-, 16-, 8-bit) SIMD FP data.
G. Paulin +13 more
semanticscholar +1 more source
Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors
IEEE Access, 2022 A lightweight block cipher PIPO-64/128 was presented in ICISC’2020. PIPO of the 8-bit unit using an unbalanced-bridge S-box showed better performance than other lightweight block cipher algorithms on an 8-bit AVR environment.
Youngbeom Kim, Seog Chung Seo
doaj +1 more source
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency [PDF]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 The ever-increasing computational and storage requirements of modern applications and the slowdown of technology scaling pose major challenges to designing and implementing efficient computer architectures.
Matteo Perotti +3 more
semanticscholar +1 more source
Backporting RISC-V Vector Assembly
, 2023 Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee +2 more
openaire +2 more sources