Results 41 to 50 of about 21,625 (285)
IEEE Access, 2020 This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
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An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications [PDF]
, 1957 This paper presents a reconfigurable cryptographic engine that implements the DTLS protocol to enable end-to-end security for IoT. This implementation of the DTLS engine demonstrates 10x reduction in code size and 438x improvement in energy-efficiency ...
Banerjee, Utsav +4 more
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Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype
Journal of Low Power Electronics and Applications, 2022 RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes
Pascal Pieper +2 more
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A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors [PDF]
, 2023 With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects.
Abolfazl Sajadi +19 more
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Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
Cryptography, 2022 The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı +2 more
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RISER: Raising RISC-V to the cloud
HiPEACInfo magazine, 2023 First public announcement of the RISER ('RISC-V for Cloud Services') project, in the HiPEACInfo magazine (issue Nr. 68, January 2023).
Marazakis, Manolis, Louloudakis, Stelios
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A Unified PUF and Crypto Core Exploiting the Metastability in Latches
Future Internet, 2022 Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations.
Ronaldo Serrano +5 more
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Design of SoC System for Convolution Acceleration Based on RISC-V Processor [PDF]
Jisuanji gongcheng, 2021 To improve the computation and energy efficiency of Convolutional Neural Network(CNN),this paper proposes a convolution accelerator with 8 bit fixed-point data as input.The accelerator supports common CNN calculations,including activation,Batch ...
ZHANG Kunning, ZHAO Shuo, HE Hu, DENG Ning, YANG Xu
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A RISC-V Processor Design for Transparent Tracing [PDF]
Electronics, 2020 Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code
Gamino del Río, Iván +7 more
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Backporting RISC-V Vector Assembly
, 2023 Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee +2 more
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