Results 61 to 70 of about 21,625 (285)
A Scalable, Portable, and Memory-Efficient Lock-Free FIFO Queue [PDF]
, 2019 We present a new lock-free multiple-producer and multiple-consumer (MPMC) FIFO queue design which is scalable and, unlike existing high-performant queues, very memory efficient.
Nikolaev, Ruslan
core +2 more sources
DEMIX: Domain-Enforced Memory Isolation for Embedded System
Sensors, 2023 Memory isolation is an essential technology for safeguarding the resources of lightweight embedded systems. This technique isolates system resources by constraining the scope of the processor’s accessible memory into distinct units known as domains ...
Haeyoung Kim +4 more
doaj +1 more source
CIDPro: Custom Instructions for Dynamic Program Diversification
, 2018 Timing side-channel attacks pose a major threat to embedded systems due to their ease of accessibility. We propose CIDPro, a framework that relies on dynamic program diversification to mitigate timing side-channel leakage.
Biswas, Arnab Kumar +4 more
core +1 more source
Porting of eChronos RTOS on RISC-V Architecture [PDF]
, 2020 11 pages, 3 figures, Accepted for Publication for Springer LNCS ...
M. Sridevi +3 more
openaire +3 more sources
FAC-V: An FPGA-Based AES Coprocessor for RISC-V
Journal of Low Power Electronics and Applications, 2022 In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads.
Tiago Gomes +4 more
doaj +1 more source
RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography
Transactions on Cryptographic Hardware and Embedded Systems, 2020 Empowering electronic devices to support Post-Quantum Cryptography (PQC) is a challenging task. PQC introduces new mathematical elements and operations which are usually not easy to implement on standard processors.
Tim Fritzmann +2 more
doaj +1 more source
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
, 2017 Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design.
Collier William W. +5 more
core +1 more source
Secure Silicon: Towards Virtual Prototyping [PDF]
, 2016 Evaluating security vulnerabilities of software implementations at design step is of primary importance for applications developers, while it has received litte attention from scientific communauty.
Sauvage, Laurent +2 more
core +1 more source
A RISC-V Processor Designed For Security [PDF]
Advanced Computing and Communications, 2019 A microprocessor is as secure as its weakest module. Depending on the application, the weakest module may be present in the hardware, micro-architecture, or a vulnerability in the software. For instance in a web-server, the biggest threats occur due to software vulnerabilities and due to information leakage in shared micro-architecture components.
Vinod Ganesan +9 more
openaire +1 more source
Molecular Oncology, EarlyView.A‐to‐I editing of miRNAs, particularly miR‐200b‐3p, contributes to HGSOC progression by enhancing cancer cell proliferation, migration and 3D growth. The edited form is linked to poorer patient survival and the identification of novel molecular targets.
Magdalena Niemira +14 more
wiley +1 more source