A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications [PDF]
Micromachines, 2023 A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme ...
Yunfeng Hu +7 more
doaj +2 more sources
Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
Active and Passive Electronic Components, 2023 This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
doaj +2 more sources
A 10-Bit 400-KS/s Low Noise Asynchronous SAR ADC with Dual-Domain Comparator for Input-Referred Noise Reduction [PDF]
Sensors, 2022 This paper presents a low noise 0.6-V 400-kS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for input-referred noise reduction. A dual-domain comparator is proposed to optimize the power, noise, and sampling rate
Sang-Hun Lee, Won-Young Lee
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A 1-GS/s 6–8-b Cryo-CMOS SAR ADC for Quantum Computing [PDF]
IEEE Journal of Solid-State Circuits, 2023 This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6–8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency ...
Gerd Kiene +7 more
openalex +2 more sources
A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications [PDF]
Micromachines, 2023 A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method.
Yunfeng Hu +8 more
doaj +2 more sources
A 100 KS/s 8–10-Bit Resolution-Reconfigurable SAR ADC for Biosensor Applications [PDF]
Micromachines, 2022 A DAC switching scheme that combines energy efficiency and resolution reconfigurability is proposed. Compared with the conventional switching scheme, the proposed scheme achieves 93.8%, 96.1%, and 97.3% switching energy saving in 8-bit, 9-bit, and 10-bit
Yunfeng Hu +5 more
doaj +2 more sources
Exploiting Smallest Error to Calibrate Non-Linearity in SAR Adcs [PDF]
IEEE Access, 2018 This paper presents a statistics-optimized organization technique to achieve better element matching in successive approximation register (SAR) analog-to-digital converter (ADC) in smart sensor systems.
Hua Fan +7 more
doaj +3 more sources
A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices [PDF]
Sensors, 2018 This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique,
Yongkui Yang +3 more
doaj +2 more sources
A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers [PDF]
IEEE Access, 2023 This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over
Hyeonsik Kim, Soohoon Lee, Jintae Kim
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Two-Step Single Slope/SAR ADC with Error Correction for CMOS Image Sensor [PDF]
The Scientific World Journal, 2014 Conventional two-step ADC for CMOS image sensor requires full resolution noise performance in the first stage single slope ADC, leading to high power consumption and large chip area.
Fang Tang +5 more
doaj +2 more sources