Results 1 to 10 of about 17,773 (197)
A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications [PDF]
Micromachines, 2023 A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme ...
Yunfeng Hu +7 more
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Exploiting Smallest Error to Calibrate Non-Linearity in SAR Adcs [PDF]
IEEE Access, 2018 This paper presents a statistics-optimized organization technique to achieve better element matching in successive approximation register (SAR) analog-to-digital converter (ADC) in smart sensor systems.
Hua Fan +7 more
doaj +3 more sources
A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications [PDF]
IEEE Access, 2019 This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution ...
Byungjoo Oh +2 more
doaj +3 more sources
SAR-Assisted Energy-Efficient Hybrid ADCs
IEEE Open Journal of the Solid-State Circuits SocietyThe distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention.
Kent Edrian Lozada +4 more
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Bandpass ΔΣ ADC using pipelined SAR ADC [PDF]
Electronics Letters, 2020 This Letter proposes a second‐order bandpass ΔΣ ADC using a pipelined successive‐approximation‐register (SAR) ADC as an internal quantiser. The second‐order bandpass noise‐shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure.
S. Oh, K. Kim, H. Chae
openaire +1 more source
IEEE Access, 2021 A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time ...
Deeksha Verma +11 more
doaj +1 more source
Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10
Jurnal Elkomika, 2022 ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA +2 more
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A 14.5-Bit ENOB, 10MS/s SAR-ADC With 2nd Order Hybrid Passive-Active Resonator Noise Shaping
IEEE Access, 2022 A new 2nd order noise shaping (NS) based successive approximation register (SAR) ADC is presented in this paper. In comparison to earlier research, this paper considers hybrid passive-active integrators to compensate for the phase error of the passive ...
Ximing Fu, Kamal El-Sankary
doaj +1 more source
Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
Active and Passive Electronic Components, 2023 This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
doaj +1 more source
Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
doaj +1 more source