Results 131 to 140 of about 2,350 (180)
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Design of the internal DAC in SAR ADCs
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), 2012This paper investigates the tradeoffs in the design of a charge-redistribution D/A converter (DAC) in successive-approximation register A/D converters. A new capacitive DAC is also introduced. It is shown that the proposed circuit can reduce the power dissipation by a factor 16, and chip area by a factor of 4, compared to a conventional DAC.
Behnam Sedighi +2 more
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Selectable starting bit SAR ADC
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015Prior work used least-significant bit first quantization (LSBFQ) to conserve switching energy and comparator bitcycles, but is limited to low activity signals. Furthermore, LSBFQ results in a large bitcycle range in the quantizer. A novel selectable starting bit quantizer (SSBQ) is proposed which starts quantization with neither the MSB nor the LSB ...
Jerry Leung, Allen Waters, Un-Ku Moon
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SAR ADC that is configurable to optimize yield
2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any ...
Tomohiko Ogawa +9 more
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Power consumption bounds for SAR ADCs
2011 20th European Conference on Circuit Theory and Design (ECCTD), 2011Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures.
Dai Zhang +2 more
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Noise Modeling and Analysis of SAR ADCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2015A generic statistical model for calculating input-referred noise of an analog-to-digital converter (ADC) impaired by thermal noise is proposed. Based on this model, detailed statistical analyses are performed on three successive approximation register (SAR) ADCs and the analytical results obtained are verified with Monte Carlo simulations.
Wenpian Paul Zhang, Xingyuan Tong
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Unified ADC nonlinearity error model for SAR ADC
Measurement, 2008Abstract The paper introduces a new ADC static nonlinearity model focusing on SAR ADC which is labelled the unified ADC nonlinearity error model. The model can also cover any other ADC architectures that have stochastic and/or periodic extremes in their integral nonlinearity function superposed on a “slowly changing” background. In the proposed model
Linus Michaeli +2 more
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Versatile SAR-ADC for Biomedical Applications
2018 New Generation of CAS (NGCAS), 2018This paper presents a versatile SAR ADC targeting the acquisition of signals in biomedical applications. The converter is implemented in a CMOS AMS 0.35µm technology and powered with 3.3V. Its output bit-width can be varied from 4 to 8 bits. The device includes built-in programmable clock generator and voltage reference circuit.
J. Sotiere +6 more
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Analog Integrated Circuits and Signal Processing, 2011
A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.
Tao Tong +2 more
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A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.
Tao Tong +2 more
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Analysis and optimization of a SAR ADC with attenuation capacitor
2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2014The conventional binary weighted array SAR ADC is the common topology adopted to achieve high efficiency conversion, i.e. with less than 10 fJ/conversion-step, even requiring extra effort to design and simulate full custom sub-fF capacitors. This paper presents the design and the optimization of an asynchronous SAR ADC with attenuation capacitor ...
BRENNA, STEFANO +4 more
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A SAR-Assisted Two-Stage Pipeline ADC
IEEE Journal of Solid-State Circuits, 2011Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations. On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex. We pro pose a two-stage pipeline ADC architecture with
Chun C. Lee, Michael P. Flynn
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