Results 151 to 160 of about 2,350 (180)
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A Predictive SAR ADC Architecture
IEEE Transactions on Circuits and Systems I: Regular PapersMatias Jara, Behzad Razavi
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Adiabatic Charging in SAR ADCs
Successive Approximation Register (SAR) is an established and well-rounded (Analog-to-Digital Converter) ADC architecture allowing for medium resolution and medium conversion speed while being energy efficient and relatively small in area. Switched-capacitor (Digital-to-Analog Converter) DAC being an essential component of the SAR architecture in ...openaire +1 more source
A Physically Unclonable Function Embedded in a SAR ADC
2022 IEEE International Test Conference in Asia (ITC-Asia), 2022Yi-Ying Chen, Soon-Jyh Chang
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An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a ...
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A 1 GS/s 10bit SAR ADC with background calibration in 28 nm CMOS
Microelectronics Journal, 2021Zheng Qiu, Lijie Yang
exaly
LMS-based digital background mismatch calibration technique for SAR ADC
Microelectronics Journal, 2023Shida Song, Yuhua Liang
exaly
Look Ahead CLS in Pipelined SAR ADCs
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022Morgan Thomas +2 more
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A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration
IEEE Journal of Solid-State Circuits, 2014Anantha P Chandrakasan
exaly
A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors
Microelectronics Journal, 2023exaly