Results 161 to 170 of about 2,350 (180)
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A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision
IEEE Transactions on Circuits and Systems II: Express Briefs, 2020Yi-Ju Roh +2 more
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An asynchronous 12-bit 50 MS/s rail-to-rail Pipeline-SAR ADC in 0.18 μm CMOS
Microelectronics Journal, 2016Shubin Liu, Zhangming Zhu
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A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC
IEEE Journal of Solid-State Circuits, 2016Chun-Cheng Liu
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A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC
IEICE Transactions on Electronics, 2016Masaya Miyahara, Akira Matsuzawa
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SAR ADC architecture with 98% reduction in switching energy over conventional scheme
Electronics Letters, 2013Arindam Sanyal
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A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
IEEE Transactions on Circuits and Systems I: Regular Papers, 2013Ying-Zu Lin +2 more
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A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18 µm CMOS
Microelectronics Journal, 2016Shubin Liu, Zhangming Zhu
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A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS
IEEE Journal of Solid-State Circuits, 2012Bob Verbruggen, Jan Craninckx
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