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A compensation technique for SAR ADC comparator noise
2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS), 2013This paper proposes a new way to compensate comparator errors in successive approximation analog-to-digital convertor (SAR ADC). The method adds negatively biased capacitance to traditional binary-scaled compensation, increasing ADC accuracy by up to 20%.
Xiao Liu, Catherine Dehollain
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2015
Chapter 2 discussed the basics of the SAR ADCs and their components such as the CDAC or the comparator in detail. Based on these fundamentals, Chap. 3 will present current research topics in the field of SAR ADCs. Generally, the core circuitry of the new SAR ADC should operate from a significantly lower supply voltage compared to the input voltage ...
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Chapter 2 discussed the basics of the SAR ADCs and their components such as the CDAC or the comparator in detail. Based on these fundamentals, Chap. 3 will present current research topics in the field of SAR ADCs. Generally, the core circuitry of the new SAR ADC should operate from a significantly lower supply voltage compared to the input voltage ...
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2019
The noise-shaping successive approximation register (NS-SAR) ADC is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the Δ Σ ADC. They have the merits of simple, highly digital, and low-voltage tolerant, making them attractive candidates for emerging sensing and
Shaolan Li +3 more
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The noise-shaping successive approximation register (NS-SAR) ADC is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the Δ Σ ADC. They have the merits of simple, highly digital, and low-voltage tolerant, making them attractive candidates for emerging sensing and
Shaolan Li +3 more
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2011
SAR ADC is the best choice for low-power and high-resolution application in signal processing systems, since it is fit to work in midst rate per conversion (MSPS, GSPS). In order to guide trade-off design better, this paper starts with analyzing the advantages and disadvantages of known FoMs (figure of merits) of traditional SAR ADC.
Libin Hu, Wenshi Li
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SAR ADC is the best choice for low-power and high-resolution application in signal processing systems, since it is fit to work in midst rate per conversion (MSPS, GSPS). In order to guide trade-off design better, this paper starts with analyzing the advantages and disadvantages of known FoMs (figure of merits) of traditional SAR ADC.
Libin Hu, Wenshi Li
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Integrated CMOS ADC — Tutorial review on recent hybrid SAR-ADCs
2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems, 2017Recently, SAR-ADC architecture is often used as an integrated ADC architecture in VLSI chip. The advantage of SAR ADC is the non-necessity of high-gain OP amps, low power consumption features, and it's suitability to fine process. On the other hand, disadvantage with simple SAR architecture, however, is its difficulty to achieve high-sampling frequency
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Evolutional of the SAR ADC Slides
2018AbstractSuccessive approximation Analog to Digital Converters (SAR ADCs) have become one of the dominant types of ADC. SAR ADCs are extremely efficient when working at moderate sampling speeds and at moderate resolutions. Through interleaving, SAR ADCs can operate at very high sampling rates.
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Evolutional of the SAR ADC Transcript
2018AbstractSuccessive approximation Analog to Digital Converters (SAR ADCs) have become one of the dominant types of ADC. SAR ADCs are extremely efficient when working at moderate sampling speeds and at moderate resolutions. Through interleaving, SAR ADCs can operate at very high sampling rates.
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Introduction of Noise-Shaping SAR ADCs
2022 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2022openaire +1 more source