Results 11 to 20 of about 582,151 (290)

A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications [PDF]

Scientific Reports
A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are
Kawther I. Arafa, Dina M. Ellaithy, Heba Shawkey, Mohamed Abouelatta, Abdelhalim Zekry   +4 more
doaj   +2 more sources

A Triple-Mode Performance-Optimized Reconfigurable Incremental ADC for Smart Sensor Applications [PDF]

IEEE Access, 2019
This paper proposes a triple-mode discrete-time incremental analog-to-digital converter (IADC) employing successive approximation register (SAR)-based zooming and extended counting (EC) schemes to achieve programmable trade-off capability of resolution ...
Byungjoo Oh, Kyeonghwan Park, Jae Joon Kim   +2 more
doaj   +3 more sources

Design and Implementation of High Speed and Low Power 12-Bit SAR ADC Using 22nm FinFET

Iranian Journal of Electrical and Electronic Engineering, 2022
Successive approximation register (SAR) analog to digital converter (ADC) architecture comprises submodules such as comparator, digital to analog converters (DAC), and SAR logic.
G. Vasudeva, B. V. Uma
doaj   +2 more sources

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems. [PDF]

Sensors (Basel), 2019
Ro D, Min C, Kang M, Chang IJ, Lee HM.
europepmc   +3 more sources

A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications. [PDF]

Micromachines (Basel), 2022
Hu Y, Tang B, Hu L, Liang H, Li B, Wu Z, Liu X.   +6 more
europepmc   +3 more sources

SAR-Assisted Energy-Efficient Hybrid ADCs

IEEE Open Journal of the Solid-State Circuits Society
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention.
Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu   +4 more
doaj   +2 more sources

Design of a Compact 5-bit SAR ADC With Voltage Interpolating Comparison for On-Chip Temperature Sensors

IEEE Access
This paper presents a cost-effective compact 5-bit successive approximation register (SAR) analog-to-digital converter (ADC) for state-of-the-art computing processor and memory applications.
Chan-Keun Kwon, Young-Jae Min
doaj   +2 more sources

Bandpass ΔΣ ADC using pipelined SAR ADC [PDF]

Electronics Letters, 2020
This Letter proposes a second‐order bandpass ΔΣ ADC using a pipelined successive‐approximation‐register (SAR) ADC as an internal quantiser. The second‐order bandpass noise‐shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure.
S. Oh, K. Kim, H. Chae
openaire   +1 more source

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

IEEE Access, 2021
A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time ...
Deeksha Verma, Behnam S. Rikan, Khuram Shehzad, Sung Jin Kim, Danial Khan, Venkatesh Kommangunta, Syed Adil Ali Shah, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee   +11 more
doaj   +1 more source

Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10

Jurnal Elkomika, 2022
ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA, HARI ARIEF DHARMAWAN, SETYAWAN PURNOMO SAKTI   +2 more
doaj   +1 more source